Abstract: A refresh circuit performs directive operation for the execution of refresh operation in response to a cycle signal cyclically output from a timer circuit provided in a command-signal activating circuit. To execute testing, a stop signal generated in response to an external signal is activated, the activated stop signal is input to an AND gate, and the cycle signal is thereby invalidated. This causes the refresh operation to terminate, thereby enabling this semiconductor memory device to refresh characteristic testing to be performed.

Abstract: A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.

Abstract: Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional static memory is provided.

Abstract: An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

Abstract: A row control circuit includes a selector for outputting, as a signal ZRXTRSTD, either signal INTSIG or ZRXTRST in accordance with a test signal TEST, and a holding circuit for receiving a signal ZRXTS by an input A, receiving the signal ZRXTRSTD by an input B, and outputting a word line activating signal RXT from an output node OUT. In a test mode, the phase relation of a sense amplifier activating signal S0N and the word line active signal RXT is set to be different from that in a normal mode. Consequently, a margin of a timing of reading operation or restoring operation can be evaluated.

Abstract: In a test mode, a first switch circuit is inactivated, and second and third switch circuits are activated. The oscillation frequency of a ring oscillator can be measured by measuring a delay value from the time a signal is input from a node inputting a test signal to the time it is output through the second switch circuit, inversion and delay circuit and the third switch circuit. Therefore, a semiconductor device capable of a simple measurement of the oscillation frequency can be provided.

Abstract: In operation, a charge pumping circuit supplies negative charges to an internal voltage line so as to reduce a negative internal voltage. A voltage dividing circuit produces a control voltage according to the difference between a first positive voltage externally applied to a first input terminal in the test mode and the internal voltage. A comparison circuit operates the charge pumping circuit according to the comparison result between a second positive voltage externally applied to a second input terminal in the test mode and the control voltage. The second positive voltage is set according to a target value of the negative internal voltage.

Abstract: A row control circuit includes a selector for outputting, as a signal ZRXTRSTD, either signal INTSIG or ZRXTRST in accordance with a test signal TEST, and a holding circuit for receiving a signal ZRXTS by an input A, receiving the signal ZRXTRSTD by an input B, and outputting a word line activating signal RXT from an output node OUT. In a test mode, the phase relation of a sense amplifier activating signal S0N and the word line active signal RXT is set to be different from that in a normal mode. Consequently, a margin of a timing of reading operation or restoring operation can be evaluated.

Abstract: In a semiconductor memory device, a refresh circuit outputs a refresh command signal for executing refresh operation. The refresh circuit includes a command-signal activating circuit for activating the refresh command signal, and a determination circuit for determining whether the activated refresh command signal is to be output. The determination circuit determines that the activated refresh command signal is to be output when the semiconductor memory device is in a standby state. Thereby, the semiconductor memory device enables stable refresh operation to be executed.

Abstract: When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.

Abstract: A refresh circuit performs directive operation for the execution of refresh operation in response to a cycle signal cyclically output from a timer circuit provided in a command-signal activating circuit. To execute testing, a stop signal generated in response to an external signal is activated, the activated stop signal is input to an AND gate, and the cycle signal is thereby invalidated. This causes the refresh operation to terminate, thereby enabling this semiconductor memory device to refresh characteristic testing to be performed.

Abstract: A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.

Abstract: Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional static memory is provided.

Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

Abstract: The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.

Abstract: A semiconductor memory includes a first decoder selecting any of modes 1-n of a test mode B according to first to fourth data signals, and a second decoder selecting any of modes 1-n of the test mode B according to fifth to eighth data signals. When a predetermined mode m+1 is not set in a test mode A, the mode selected by both the first and second decoders is set. When the predetermined mode m+1 is set, the mode selected by the first decoder is set. Therefore, the test mode B can be set at the manufacturer side by connecting only four data input/output terminals to the tester.

Abstract: In a test mode, a first switch circuit is inactivated, and second and third switch circuits are activated. The oscillation frequency of a ring oscillator can be measured by measuring a delay value from the time a signal is input from a node inputting a test signal to the time it is output through the second switch circuit, inversion and delay circuit and the third switch circuit. Therefore, a semiconductor device capable of a simple measurement of the oscillation frequency can be provided.

Abstract: An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

Abstract: A stable internal clock signal generator capable of suppressing an oscillation caused by a fluctuation in a power source or the like. A shift register 14 stores a binary comparison result indicating whether a phase obtained by a comparison carried out through a phase comparing circuit 13 past (n+1) times is advanced or delayed, a phase control circuit 15 outputs, as a phase control signal to a phase variable circuit 12, the larger number of comparison results obtained by carrying out the comparison (n+1) times, and the phase variable circuit 12 adjusts the phase of an internal clock signal intclk based on the input phase control signal.