Abstract: Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

Abstract: The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.

Abstract: An interlayer insulating layer is formed to cover a fuse layer. A concave portion is provided on the surface of interlayer insulating layer located directly above fuse layer. A nitride layer as a passivation layer extends on the sidewalls of concave portion. In this way, a semiconductor device is obtained, the device having an improved moisture resistance, and in which a fuse can be easily blown by laser and a design rule of the region adjacent to the fuse can be improved.

Abstract: An input signal phase compensation circuit having a monitor mode and a normal operation mode includes a mode switching circuit, a logic gate receiving an internal data signal, a delay circuit connected to the logic gate, and a phase comparator comparing, in the monitor mode, phases of a signal output from the delay circuit and a clock signal, and determining time for delaying an internal clock signal in a variable delay circuit so as to match phases of the both signals. In the normal operation mode, the time is fixed, and data is obtained at phase compensated timing.

Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Abstract: A semiconductor integrated circuit device of the present invention includes a plurality of banks and a plurality of sense amplifier bands. A switch circuit included in each sense amplifier band receives a signal on a transmission line and outputs a signal read from the bank to a global data input/output line arranged in the column direction. A column bank control circuit for outputting a column bank control signal is arranged on the column decoder side. The column bank control signal is supplied to the transmission line through a column bank control signal line arranged in the column direction. The switch circuit operates in accordance with the column bank control signal. By such a configuration, a column-related operation can be matched easily.

Abstract: On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

Abstract: Conductive lines for electrostatic shielding including at least one signal line are arranged between a global data I/O bus line and a ground line transmitting a ground voltage to a nonselected word line through a sub-decoder. Capacitive coupling between bus lines included in the global data I/O bus and the ground line is suppressed, and floating up of a ground voltage on the nonselected word line is prevented.

Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

Abstract: Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

Abstract: A semiconductor integrated circuit device realizing high speed operation and low current consumption and ensure reliability evaluation is provided. Reference voltage generating circuits for generating reference voltages of mutually different voltage levels are provided for power supply pads respectively, and voltage down converters for down converting power supply voltages of corresponding external power supply pads to corresponding reference voltage levels and transmitting the lowered voltages to corresponding internal power supply lines are provided corresponding to respective reference voltage generating circuits. Further, a switching transistor is provided at an output node of the reference voltage generating circuit which is rendered conductive at a stress acceleration mode for connecting the corresponding external power supply pad to the output node of the corresponding reference voltage generating circuit.

Abstract: A memory device having a smaller circuit area but efficiently used is provided. A plurality of main word lines (MWL) extending in a row direction are connected through respective bank latches (BL) to a single global word line (GWL) extending across banks (BANK0, BANK1). Selective activation of an enable signal (BLE) and the global word line (GWL) selects one of the bank latches (BL) to selectively activate an associated main word line (MWL). This state is held by the selected bank latch (BL) after the enable signal (BLE) is inactivated. Then, another enable signal (BLE) is activated to selectively activate another main word line (MWL). Sub-decoders (SD) connected to the main word lines (MWL) are selected independently of each other to independently activate word lines (WL) for each bank (BANK).

Abstract: A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.

Abstract: In a defective cell write mode, a precharge potential generating circuit generates a precharge potential at a high level or a low level in accordance with an external control signal, and applies the potential to a bit line pair. Parallel to a fuse element provided between a main bit line precharge potential supply line and a sub bit line precharge potential supply line and is cut when a column is replaced by a redundancy column of memory cells, a pass transistor which is rendered conductive in the defective cell write mode is provided.

Abstract: Memory mats provided in four regions formed by dividing a semiconductor chip are each further divided into a plurality of memory arrays along the longer side direction of the chip, row related circuits are provided between the memory arrays along the shorter side direction of the chip, and column decoders are provided along the longer side direction of the chip. An internal control signal from a master control circuit in the central part of the chip is transmitted in the central region with respect to the shorter side direction of the chip, buffer circuits are provided to an internal control signal transmission bus, and an internal signal is transmitted to the row related circuit and the column decoder by the buffer circuit. The length of the signal line to drive is shortened, and therefore the signal can be transmitted at a high speed, thus enabling high speed accessing. Thus, signal propagation delay can be reduced even if the chip size increases.

Abstract: Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

Abstract: In a semiconductor integrated circuit device, a voltage setting circuit for setting a voltage level on the sub power source voltage line according to a reference voltage from a reference voltage generating circuit, is provided between a main power source voltage line and a sub power source voltage line. While a current consumption at the standby cycle is reduced, increase of the access delay is prevented. The voltage setting circuit includes a differential amplifier for differentially amplifying a voltage on the sub power source line and the reference voltages and a transistor responsive to an output of the differential amplifier for causing a current flow between the main and sub power source lines, or alternatively a diode-connected insulated gate type transistor receiving the reference voltage at a back gate thereof.

Abstract: In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

Abstract: Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.