Patents by Inventor Masaki Yamato

Masaki Yamato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200300889
    Abstract: A first signal line pattern has one end electrically connected to a first connector. A second signal line pattern has one end electrically connected to a second connector. The second signal line pattern has the other end facing the other end of the first signal line pattern. A conductive block has a convex portion. The convex portion of the conductive block is electrically connected to a third portion of the conductive pattern positioned between the other end of the first signal line pattern and the other end of the second signal line pattern of the wiring board.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 24, 2020
    Applicant: YOKOWO CO., LTD.
    Inventors: Masaki NOGUCHI, Takahiro NAGATA, Tsuyoshi YAMATO
  • Patent number: 10074694
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Patent number: 9905759
    Abstract: According to one embodiment, a memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Patent number: 9728585
    Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate which extends in first and second directions that intersect each other; a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second direction, and which extend in the first direction; a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells having a first film whose resistance changes electrically, a thickness in the second direction of the first film changing with respect to a change of position in the third direction, and the first films of two of the memory cells adjacent in the third direction being separated between the two memory cells.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: August 8, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Takeshi Yamaguchi, Takeshi Takagi, Natsuki Fukuda
  • Patent number: 9679947
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: June 13, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20170133586
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 11, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Yasuhiro NOJIRI, Shigeki KOBAYASHI, Hiroyuki FUKUMIZU, Takeshi YAMAGUCHI
  • Publication number: 20170117039
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a memory cell array; and a control circuit that manages a setting operation and a read operation. The memory cell array comprises: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell including a variable resistance element and a nonlinear element. The variable resistance element is configured having a first metal film, a first variable resistance film, a second variable resistance film, and a second metal film stacked and disposed therein in this order. A work function of the second metal film is smaller than a work function of the first metal film.
    Type: Application
    Filed: March 15, 2016
    Publication date: April 27, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Takeshi YAMAGUCHI, Takeshi TAKAGI, Hiroyuki ODE, Toshiharu TANAKA
  • Patent number: 9634064
    Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: April 25, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Takeshi Yamaguchi, Shigeki Kobayashi
  • Patent number: 9590016
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: March 7, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20170062713
    Abstract: According to one embodiment, A memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.
    Type: Application
    Filed: February 2, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
  • Patent number: 9559300
    Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Ode, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
  • Publication number: 20170025475
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Application
    Filed: February 8, 2016
    Publication date: January 26, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
  • Publication number: 20160260479
    Abstract: A semiconductor memory device comprises: a memory cell array 11; and a control circuit 16 that controls a voltage applied to the memory cell array 11. The memory cell array 11 includes: a plurality of word lines WL and bit lines BL that intersect each other; and a memory cell MC disposed at each of intersections of these word lines WL and bit lines BL. The memory cell MC includes a variable resistance element VR and a non-ohmic element NO. The variable resistance element VR is formed by a hafnium oxide crystalline film of monoclinic crystal in which a proportion of a component oriented in a (?1, 1, 1) plane and a (1, 1, 1) plane is 90% or more. This hafnium oxide crystalline film can be manufactured by a film-forming process by atomic layer deposition, employing an inorganic type hafnium precursor.
    Type: Application
    Filed: September 3, 2015
    Publication date: September 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuiki ODE, Takeshi YAMAGUCHI, Takeshi TAKAGI, Toshiharu TANAKA, Masaki YAMATO
  • Publication number: 20160254319
    Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Takeshi YAMAGUCHI, Shigeki KOBAYASHI
  • Patent number: 9418737
    Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Takagi, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
  • Publication number: 20160189776
    Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.
    Type: Application
    Filed: July 30, 2015
    Publication date: June 30, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi TAKAGI, Masaki YAMATO, Hiroyuki ODE, Takeshi YAMAGUCHI, Toshiharu TANAKA
  • Patent number: 9362500
    Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 7, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Yamato, Takeshi Yamaguchi, Shigeki Kobayashi
  • Patent number: 9336880
    Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: May 10, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Takagi, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
  • Publication number: 20160099289
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Patent number: 9246088
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: January 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi