Patents by Inventor Masaki Yamato

Masaki Yamato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160019959
    Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.
    Type: Application
    Filed: March 2, 2015
    Publication date: January 21, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
  • Patent number: 9224788
    Abstract: According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Takeshi Yamaguchi, Masaki Yamato, Yoshinori Nakakubo, Hiroyuki Ode
  • Patent number: 9209394
    Abstract: According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Ode, Takeshi Yamaguchi, Masaki Yamato, Shigeki Kobayashi, Yoshinori Nakakubo
  • Publication number: 20150295174
    Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
    Type: Application
    Filed: June 24, 2015
    Publication date: October 15, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Takeshi YAMAGUCHI, Shigeki KOBAYASHI
  • Publication number: 20150263278
    Abstract: A memory device according to an embodiment, includes a selection element, a first interconnection provided in a first direction when viewed from the selection element and extending in the first direction, a plurality of second interconnections provided in a second direction crossing the first direction when viewed from the first interconnection and arranged in the first direction, a memory element provided between the first interconnection and the second interconnection, and a high resistance component connected between the selection element and the first interconnection and having a resistivity higher than a resistivity of the first interconnection and a resistivity of the second interconnection.
    Type: Application
    Filed: September 19, 2014
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki ODE, Takeshi YAMAGUCHI, Shigeki KOBAYASHI, Masaki YAMATO, Yoshinori NAKAKUBO, Takeshi TAKAGI, Takayuki TSUKAMOTO
  • Publication number: 20150255513
    Abstract: In accordance with an embodiment, a semiconductor memory device includes a substrate, first and second wirings on the substrate across each other, and a storage element at an intersection of the first and second wirings between the first and second wirings. The storage element includes first and second electrodes having first and second materials, respectively, a first film having a first dielectric constant, and a second film having a second dielectric constant lower than the first dielectric constant. The first film is formed on the first electrode. The second electrode is formed on the first film. The second film is disposed between the second electrode and the first film. An energy difference between a vacuum level and a Fermi level of the second material is equal to or more than an energy difference between the vacuum level and a Fermi level of the first material.
    Type: Application
    Filed: June 17, 2014
    Publication date: September 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori NAKAKUBO, Shigeki Kobayashi, Takeshi Yamaguchi, Hiroyuki Ode, Masaki Yamato
  • Patent number: 9099648
    Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: August 4, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Yamato, Takeshi Yamaguchi, Shigeki Kobayashi
  • Publication number: 20150207071
    Abstract: In accordance with an embodiment, a manufacturing method of a resistive element film includes sequentially repeating, a desired number of times, first and second film formation cycles. In the first film formation cycle, an insulating film is formed up to a continuous layer by an ALD film formation method under a first condition. In the second film formation cycle a metal film is formed on the insulating film up to a continuous layer by the ALD film formation method under a second condition.
    Type: Application
    Filed: June 9, 2014
    Publication date: July 23, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki ODE, Takeshi Yamaguchi, Shigeki Kobayashi, Masaki Yamato, Yoshinori Nakakubo
  • Publication number: 20150155333
    Abstract: According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film.
    Type: Application
    Filed: March 13, 2014
    Publication date: June 4, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki KOBAYASHI, Takeshi YAMAGUCHI, Masaki YAMATO, Yoshinori NAKAKUBO, Hiroyuki ODE
  • Patent number: 9018613
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shigeki Kobayashi, Masaki Yamato
  • Publication number: 20150108420
    Abstract: According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material.
    Type: Application
    Filed: February 25, 2014
    Publication date: April 23, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki ODE, Takeshi YAMAGUCHI, Masaki YAMATO, Shigeki KOBAYASHI, Yoshinori NAKAKUBO
  • Patent number: 9013912
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory layers; and a control unit configured to control a voltage applied to the memory cell array. Each of the memory layers comprises a first line and a second line, and further includes a memory cell disposed between the first line and the second line and including a variable resistance element. The control unit is configured to, when executing a forming operation on the memory cell array, execute the forming operation sequentially on the plurality of memory layers. The forming operation is executed sequentially on the memory layers in ascending order of a magnitude of a non-selected current flowing in a non-selected memory cell during the forming operation.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Shigeki Kobayashi, Masaki Yamato, Hiroyuki Fukumizu
  • Patent number: 9007809
    Abstract: A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second electrode is configured by a P type semiconductor. The control unit, when performing a setting operation of a memory cell, applies a voltage such that a current flows in a direction from the first electrode toward the second electrode.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Fukumizu, Shigeki Kobayashi, Yasuhiro Nojiri, Masaki Yamato, Takeshi Yamaguchi
  • Publication number: 20150083989
    Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 26, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki ODE, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
  • Patent number: 8971092
    Abstract: A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Patent number: 8916846
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Takeshi Yamaguchi, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu
  • Patent number: 8912521
    Abstract: First conductive layers extend in a first direction horizontal to a substrate as a longitudinal direction, and are stacked in a direction perpendicular to a substrate. An interlayer insulating layer is provided between the first conductive layers. The variable resistance layers functioning as a variable resistance element are formed continuously on the side surfaces of the first conductive layers and the interlayer insulating layer. A columnar conductive layer is provided on the side surfaces of the first conductive layers and the interlayer insulating layer via the variable resistance layers. First side surfaces of the first conductive layers are recessed from a second side surface of the interlayer insulating layer in the direction away from the columnar conductive layers.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shigeki Kobayashi, Masaki Yamato
  • Publication number: 20140326939
    Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
    Type: Application
    Filed: September 11, 2013
    Publication date: November 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Takeshi Yamaguchi, Shigeki Kobayashi
  • Publication number: 20140241037
    Abstract: A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.
    Type: Application
    Filed: September 9, 2013
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeki KOBAYASHI, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20140209853
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Application
    Filed: September 13, 2013
    Publication date: July 31, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Yasuhiro Nojiri, Shiegeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi