Abstract: It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer.

Abstract: A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract: An object is to detect reflected light from an object accurately and to improve accuracy of capturing an image in a photosensor included in a display panel. In the display panel including a photosensor, when an image of an object is captured, light is emitted from a light source to the object and reflected light enters the photosensor. In the case where the incident light is too strong with respect to sensitivity of the photosensor, luminance of the light source is lowered. In the case where the incident light is too weak with respect to sensitivity of the photosensor, the luminance of the light source is increased.

Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Abstract: To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.

Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Abstract: An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal.

Abstract: An object is to provide an image processing circuit adaptable to displays having a variety of pixel numbers. The image processing circuit includes a data adjustment circuit, a first line memory and a second line memory capable of storing K pieces of data, an output timing control circuit, and an arithmetic circuit. To the data adjustment circuit, (X×Y) pieces of pixel data are input. Y pieces of pixel data are transmitted to the first line memory. When Y is less than K, (K?Y) pieces of dummy data are added to fill the first line memory. Then, the K pieces of data are output from the first line memory to the second line memory and a new set of K data is input to the first line memory. The arithmetic circuit stores the data input from the line memories and performs filtering.

Abstract: A memory device capable of being operated with a single potential uses capacitive coupling of a capacitor connected to a gate of a transistor for data writing. That is, the capacitive coupling is induced by inputting a signal, which is supplied by a delay circuit configured to delay a write signal having a potential equal to the power supply potential, to the capacitor. Increase in the potential of the gate by the capacitive coupling allows the transistor to be turned on in association with the power supply potential applied to the gate from a power supply. Data is written by inputting a signal having a potential equal to the power supply potential or a grounded potential to a node through the transistor.

Abstract: A semiconductor device that has a simple peripheral circuit configuration, is unlikely to deteriorate due to repetitive data writing operations, and is used as a nonvolatile switch. Even when supply of a power supply voltage is stopped, data on a conduction state is held in a data retention portion connected to a thin film transistor including an oxide semiconductor layer having a channel formation region. The data retention portion is connected to a gate of a field-effect transistor in a current amplifier circuit (in which the field-effect transistor and a bipolar transistor are connected as a Darlington pair), and thus the conduction state is controlled without leaking charge in the data retention portion.

Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Abstract: A semiconductor device is provided with a power supply circuit having a function to generate a power supply voltage from a wireless signal and an A/D converter circuit having a function to detect the strength of the wireless signal by an A/D conversion of a voltage generated from the wireless signal. This enables to provide a semiconductor device which does not require replacement of batteries, has few limitations on its physical shape and mass, and has a function to detect a physical position. By formation of the semiconductor device with use of a thin film transistor formed over a plastic substrate, a lightweight semiconductor device, which has flexibility in physical shape and a function to detect a physical location, can be provided at low cost.

Abstract: An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal.

Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract: The semiconductor memory device includes: a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer; a capacitor for storing electric charge for reading data retained in the memory circuit; a charge storage circuit for controlling storage of electric charge in the capacitor; a data detection circuit for controlling data reading; a timing control circuit for generating a first signal controlling storage of electric charge in the capacitor (storage is conducted with the charge storage circuit, and the first signal is generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a period immediately after the supply of the supply voltage); an inverter circuit for outputting a potential obtained by inverting a potential of one electrode of the capacitor.

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract: A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.

Abstract: Objects of the invention are to provide a clock generation circuit and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.