Patents by Inventor Masamichi Fujito
Masamichi Fujito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9026823Abstract: A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.Type: GrantFiled: August 26, 2010Date of Patent: May 5, 2015Assignee: Renesas Electronics CorporationInventors: Mamoru Sakugawa, Masamichi Fujito, Jun Setogawa, Masaru Takahashi, Shinsuke Yoshimura
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Publication number: 20140198577Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: March 16, 2014Publication date: July 17, 2014Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATIONInventors: Toshihiro TANAKA, Yukiko UMEMOTO, Mitsuru HIRAKI, Yutaka SHINAGAWA, Masamichi FUJITO, Kazufumi SUZUKAWA, Hiroyuki TANIKAWA, Takashi YAMAKI, Yoshiaki KAMIGAKI, Shinichi MINAMI, Kozo KATAYAMA, Nozomu MATSUZAKI
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Patent number: 8698224Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: April 20, 2013Date of Patent: April 15, 2014Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Publication number: 20130235668Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: April 20, 2013Publication date: September 12, 2013Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATIONInventors: Toshihiro TANAKA, Yukiko UMEMOTO, Mitsuru HIRAKI, Yutaka SHINAGAWA, Masamichi FUJITO, Kazufumi SUZUKAWA, Hiroyuki TANIKAWA, Takashi YAMAKI, Yoshiaki KAMIGAKI, Shinichi MINAMI, Kozo KATAYAMA, Nozomu MATSUZAKI
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Patent number: 8478929Abstract: To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device. In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.Type: GrantFiled: December 10, 2010Date of Patent: July 2, 2013Assignee: Renesas Electronics CorporationInventors: Yasunobu Aoki, Hideo Kasai, Masamichi Fujito, Junpei Inoue
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Publication number: 20130145190Abstract: A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.Type: ApplicationFiled: August 26, 2010Publication date: June 6, 2013Applicant: Renesas Electronics CorporationInventors: Mamoru Sakugawa, Masamichi Fujito, Jun Setogawa, Masaru Takahashi, Shinsuke Yoshimura
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Patent number: 8426904Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: September 1, 2011Date of Patent: April 23, 2013Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 8144518Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: May 3, 2011Date of Patent: March 27, 2012Assignee: Renesas Electronics CorporationInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Publication number: 20110309428Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: September 1, 2011Publication date: December 22, 2011Inventors: TOSHIHIRO TANAKA, Yukiko UMEMOTO, Mitsuru HIRAKI, Yutaka SHINAGAWA, Masamichi FUJITO, Kazufumi SUZUKAWA, Hiroyuki TANIKAWA, Takeshi YAMAKI, Yoshiaki KAMIGAKI, Shinichi MINAMI, Kozo KATAYAMA, Nozomu MATSUZAKI
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Publication number: 20110288807Abstract: The present invention is directed to improve the precision of failure detection by performing the failure detection by changing an analog amount of a circuit to be subjected to the failure detection. An analog amount of the circuit to be subjected to failure detection is changed under a predetermined condition by a tuning circuit, and a state change in the circuit to be subjected to failure detection based on the change in the analog amount in the circuit to be subjected to failure detection is determined by a failure detection circuit, thereby detecting a failure in the circuit to be subjected to failure detection. In such a manner, without monitoring an output of the failure detection circuit on the outside of a semiconductor device, a failure in the circuit to be subjected to failure detection can be detected.Type: ApplicationFiled: May 19, 2011Publication date: November 24, 2011Inventors: Takashi Iwase, Masamichi Fujito
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Patent number: 8017986Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: March 5, 2010Date of Patent: September 13, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Publication number: 20110208904Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Publication number: 20110145521Abstract: To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device. In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.Type: ApplicationFiled: December 10, 2010Publication date: June 16, 2011Inventors: Yasunobu AOKI, Hideo Kasai, Masamichi Fujito, Junpei Inoue
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Patent number: 7957195Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: December 3, 2009Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Publication number: 20100157689Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: March 5, 2010Publication date: June 24, 2010Inventors: TOSHIHIRO TANAKA, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 7700992Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: June 19, 2008Date of Patent: April 20, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Publication number: 20100080058Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: ApplicationFiled: December 3, 2009Publication date: April 1, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Patent number: 7646642Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: October 9, 2007Date of Patent: January 12, 2010Assignee: Renesas Technology Corp.Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Publication number: 20090254696Abstract: The semiconductor IC has a nonvolatile memory including twin cells, a selector, and a sense circuit. When complementary data are written into a pair of nonvolatile memory cells of each twin cell, the pair of nonvolatile memory cells is set to be in a written state where one cell of the pair is set to one of low and high threshold voltages, and the other is set to the other threshold voltage. When non-complementary data are written into a pair of nonvolatile memory cells, for example, the memory cells both take the low threshold voltage and are made blank. The selector includes switching elements. During the blank-check action, switching elements of the selector are controlled to ON state. Then, the first total current of the twin cells forced to flow into the first input terminal of the sense circuit commonly is compared with the reference signal on the second input terminal, whereby whether the twin cells have been written or blank can be detected at a high speed.Type: ApplicationFiled: April 3, 2009Publication date: October 8, 2009Inventors: Hideo KASAI, Masamichi Fujito, Masayuki Hirasawa
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Publication number: 20090010072Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: June 19, 2008Publication date: January 8, 2009Inventors: Toshihiro TANAKA, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki