Abstract: A memory cell of a dynamic storage device is composed of a MOSFET and a capacitor. On a single semiconductor substrate, a plurality of such memory cells are regularly arranged so as to form a plurality of columns, with the result that they constitute a memory cell array or a memory cell mat. The capacitor for the memory cell is made up of a semiconductor region of the type which possesses a conductivity opposite to that of the semiconductor substrate, and a conductor film which is formed of polycrystalline silicon or the like on the semiconductor region through a comparatively thin insulating film. The areas of the capacitors in the memory cell column situated at an end portion of the memory cell mat are made larger than those of the capacitors of the memory cells at an inner or central portion of the memory cell mat. The memory cells at the end portion of the memory cell mat come to have information holding times equivalent to those of the memory cells at the central portion of the memory cell mat.

Abstract: In a n-channel (or p-channel) random access memory in which a plurality of memory cells are arranged in a matrix form in a p-type (or n-type) semiconductor substrate, clamping MOSFET's are connected between word lines provided for the associated rows of memory cells of the matrix and a reference potential to which gates the source electrodes of the information storing MOSFET's of the memory cells are connected. The clamping MOSFET has a lower threshold voltage than a row selecting MOSFET connected to the word line and clamps the word line when the word line is not selected, so that a delay in the read-out operation is eliminated or suppressed.