Patents by Inventor Masamitsu Matsuura

Masamitsu Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178125
    Abstract: In a described example, an apparatus includes: a metal leadframe including a dielectric die support formed in a central portion of the leadframe, and having metal leads extending from the central portion, portions of the metal leads extending into the central portion contacted by the dielectric die support; die attach material over the dielectric die support; a semiconductor die mounted to the dielectric die support by the die attach material, the semiconductor die having bond pads on a device side surface facing away from the dielectric die support; electrical connections extending from the bond pads to metal leads of the leadframe; and mold compound covering the semiconductor die, the electrical connections, the dielectric die support, and portions of the metal leads, the mold compound forming a package body.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventor: Masamitsu Matsuura
  • Publication number: 20240178329
    Abstract: In examples, a semiconductor package comprises a semiconductor die including an ambient light sensor, the ambient light sensor facing a horizontal direction. The package includes first and second conductive terminals wirebonded to the semiconductor die, each of the first and second conductive terminals having first and second segments. The package includes a clear mold compound covering the semiconductor die and portions of the first and second conductive terminals. The first segments of the first and second conductive terminals extend vertically through the clear mold compound to an exterior of the clear mold compound, and wherein the second segments of the first and second conductive terminals are positioned exterior to the clear mold compound, extend horizontally in opposing directions, and are adapted to be coupled to a printed circuit board.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventor: Masamitsu MATSUURA
  • Publication number: 20240178164
    Abstract: An electronic device includes a semiconductor substrate having a first conductive routing structure on a first side of the semiconductor substrate, and a low aspect ratio via opening extending from the first side to an opposite second side. The electronic device includes a transparent cover over a portion of the first side and covering the patterned first conductive routing structure, as well as an insulator layer including a photo-imageable material on the second side and along a sidewall of the via opening, and a second conductive routing structure on an outer side of the insulator layer and extending through the via opening and directly contacting a portion of the first conductive routing structure.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Masamitsu Matsuura, Kengo Aoya, Daiki Komatsu, Ko Shibata
  • Publication number: 20240178104
    Abstract: An electronic device includes a leadframe that includes pins, where the pins have a proximate end and a distal end. A die is attached to the proximate end of the pins of the leadframe and a mold compound encapsulates the die. An electronic component is attached to the leadframe. The distal end of at least two of the pins are substantially perpendicular to the proximate end of the pins in a first direction and the distal end of the remaining pins are substantially perpendicular to the proximate end of the pins in a second direction that is opposite that of the first direction.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: MAKOTO SHIBUYA, DAIKI KOMATSU, MASAMITSU MATSUURA
  • Patent number: 11942384
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Patent number: 11923320
    Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tomoko Noguchi, Mutsumi Masumoto, Kengo Aoya, Masamitsu Matsuura
  • Patent number: 11848244
    Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: December 19, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya
  • Publication number: 20230396230
    Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: Anindya PODDAR, Hau NGUYEN, Masamitsu MATSUURA
  • Publication number: 20230275007
    Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Inventors: Makoto SHIBUYA, Masamitsu Matsuura, Kengo Aoya, Anindya Poddar
  • Patent number: 11736085
    Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 22, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Hau Nguyen, Masamitsu Matsuura
  • Publication number: 20230137762
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Publication number: 20230095630
    Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Makoto SHIBUYA, Masamitsu MATSUURA, Kengo AOYA
  • Publication number: 20230068748
    Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for receiving a semiconductor die, and having conductive leads spaced from the die pad; a semiconductor die mounted on the die pad, the semiconductor die having bond pads on an active surface configured for making electrical connections; electrical connections coupling the bond pads of the semiconductor die to the conductive leads; mold compound covering a portion of the package substrate, the semiconductor die, and the electrical connections, with the leads extending through the mold compound and having end portions exposed from the mold compound; and the leads having a first portion with a first width and extending with the first width from the mold compound to a second portion having a second width that greater than the first width.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventor: Masamitsu Matsuura
  • Publication number: 20230005881
    Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 5, 2023
    Inventors: Anindya Poddar, Mahmud Chowdhury, Hau Nguyen, Masamitsu Matsuura, Ting-Ta Yen
  • Patent number: 11410875
    Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 9, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hau Thanh Nguyen, Woochan Kim, Yi Yan, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Masamitsu Matsuura, Kengo Aoya, Mutsumi Masumoto
  • Publication number: 20220208689
    Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Tomoko NOGUCHI, Mutsumi MASUMOTO, Kengo AOYA, Masamitsu MATSUURA
  • Publication number: 20220069795
    Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 3, 2022
    Inventors: Anindya PODDAR, Hau NGUYEN, Masamitsu MATSUURA
  • Patent number: 11183441
    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
  • Patent number: 11158595
    Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
  • Publication number: 20210125959
    Abstract: In some examples, a wafer chip scale package (WCSP) comprises a die; multiple electrically conductive terminals coupled to a first surface of the die; and a metal covering abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Inventors: Masamitsu MATSUURA, Kengo AOYA, Mutsumi MASUMOTO