Patents by Inventor Masamitsu Matsuura

Masamitsu Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10580715
    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
  • Publication number: 20200058570
    Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Inventors: Kengo Aoya, Masamitsu Matsuura, Takeshi Onogami, Hideaki Matsunaga
  • Publication number: 20190385924
    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
  • Publication number: 20190013288
    Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 10, 2019
    Inventors: WOOCHAN KIM, MASAMITSU MATSUURA, MUTSUMI MASUMOTO, KENGO AOYA, HAU THANH NGUYEN, VIVEK KISHORECHAND ARORA, ANINDYA PODDAR
  • Publication number: 20160240392
    Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Anindya Poddar, Mark Allen Gerber, Mutsumi Masumoto, Masamitsu Matsuura, Kengo Aoya, Takeshi Onogami
  • Publication number: 20150147845
    Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventors: Anindya Poddar, Mark Allen Gerber, Mutsumi Masumoto, Masamitsu Matsuura, Kengo Aoya, Takeshi Onogami
  • Publication number: 20150008566
    Abstract: A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (292); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (293); laminating low CTE insulating material to fill gaps between chips and grid (294); turning over assembly to place carrier under backside of chips and lamination and to remove tape (295); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (296); optionally plating metal layer (297); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (298).
    Type: Application
    Filed: July 1, 2014
    Publication date: January 8, 2015
    Inventors: Mark A. Gerber, Mutsumi Masumoto, Kenji Masumoto, Anindya Poddar, Kengo Aoya, Masamitsu Matsuura, Takeshi Onogami
  • Patent number: 5785140
    Abstract: The present invention provides a vehicular vibration isolating apparatus, in which an upper tank of a radiator is carried, via an upper bush of an elastic material, on an upper bracket installed to an upper member on a vehicle body side, and a lower tank of the radiator is carried, via a lower bush of an elastic material, on a lower bracket installed to a lower member on the vehicle body side. In addition, gaps are formed between the upper bracket and the upper bush, and a spring for elastically supporting the radiator is installed between the lower tank and the lower bracket. As such, a dynamic damper is formed by means of the radiator, components connected to the radiator, and the spring.
    Type: Grant
    Filed: January 2, 1996
    Date of Patent: July 28, 1998
    Assignee: Suzuki Motor Corporation
    Inventors: Takehiro Suzuki, Masamitsu Matsuura