Abstract: A reachable range calculation apparatus for computing a range that a vehicle traveling on stored energy is able to reach, comprising: a storage part for storing beforehand information on a required amount of energy consumed when the vehicle moves, using each of a plurality of areas into which a map has been divided as a unit; an integration part for integrating, with respect to movement of the vehicle from a specified origin to a surrounding area, a required amount of energy on the basis of the required amount of energy stored in the storage part, each time the vehicle moves between areas; and a range determination part for determining, on the basis of a provided specified amount of energy and an integrated required amount of energy obtained by the integration part integrating energy-consumption amounts, a reachable range, which is a range of areas that the vehicle is able to reach using the specified amount of energy.

Abstract: A reachable range calculation apparatus for computing a range that a vehicle traveling on stored energy is able to reach, comprising: a storage part for storing beforehand information on a required amount of energy consumed when the vehicle moves, using each of a plurality of areas into which a map has been divided as a unit; an integration part for integrating, with respect to movement of the vehicle from a specified origin to a surrounding area, a required amount of energy on the basis of the required amount of energy stored in the storage part, each time the vehicle moves between areas; and a range determination part for determining, on the basis of a provided specified amount of energy and an integrated required amount of energy obtained by the integration part integrating energy-consumption amounts, a reachable range, which is a range of areas that the vehicle is able to reach using the specified amount of energy.

Abstract: A vehicle drive support system, and its method, includes a storage apparatus for storing charging station information to manage attribute information containing position information of charging stations, a communication apparatus for receiving a route search request containing an origin, a destination, and a residual quantity in a battery from a mobile and transmitting a response to the route search request, and a route search processing unit for searching a route passing through the charging stations while maintaining a state in which the residual quantity in the battery is greater than 0 between the origin and the destination by using position information of the charging stations contained in the charging station information in response to the route search request received by the communication apparatus, and giving the searched route as the response to the route search request.

Abstract: An object of the present information is to search for a route taking into account the charging times in the charging stations. When an electric automobile provided with a battery cannot reach a second point from a first point without the battery being charged in a charging station halfway, a route-search processing section specifies one or two or more charging stations, which the electric automobile is to pass through in order to reach the second point from the first point in a shorter time including a charging time in each of the charging stations and moving times among the charging stations, and derives a route for reaching the second point from the first point passing through the specified charging stations.

Abstract: A storage part stores beforehand, as an energy consumption graph, amounts of energy consumed by a vehicle traveling in both directions along road links on a map. A processing part traces a road link from a specified start point location peripherally, calculates, for each road node, a first and second integration values obtained by integrating amounts of energy in a direction moving away from the start point location on the energy consumption graph and in a direction moving toward the start point location on the energy consumption graph, and based on a relationship between the sum of the first integration value and the second integration value, and a given specified amount of energy for each road node, decides a round-trip driving range which is a range within which the vehicle is able to return to the start point location by using the specified amount of energy.

Abstract: In a charging control system, electrically-driven vehicles whose charging levels are lower than such a charging level required to drive these electrically-driven vehicles over a necessary minimum drivable distance are charged with a priority, and such an electrically-driven vehicle whose charging level quickly reaches the above-explained charging level among these electrically-driven vehicles is charged with a top priority. Also, in the charging control system, an order for dynamically charging vehicle-purpose batteries is rearranged by monitoring a change in charging environments, for instance, an electrically-driven vehicle is newly coupled to a charger in a half way; a commonly available electric power amount is increased by solar power generation etc.; and a supplyable electric power amount (W) is lowered due to utilization of electricity by a subject other than electrically-driven vehicles.

Abstract: A vehicle drive support system, and its method, includes a storage apparatus for storing charging station information to manage attribute information containing position information of charging stations, a communication apparatus for receiving a route search request containing an origin, a destination, and a residual quantity in a battery from a mobile and transmitting a response to the route search request, and a route search processing unit for searching a route passing through the charging stations while maintaining a state in which the residual quantity in the battery is greater than 0 between the origin and the destination by using position information of the charging stations contained in the charging station information in response to the route search request received by the communication apparatus, and giving the searched route as the response to the route search request.

Abstract: According to one aspect of wireless communication control apparatus and method for a mobile object according to the present invention, the wireless communication apparatus and method include the steps of: collecting communication-state information corresponding to positional information of the mobile object for each of a plurality of communication methods that are used to make a connection to a wireless communication device of the mobile object, and that can be selectively set in the wireless communication device; referring to the communication-state information corresponding to the positional information indicating a current position of the mobile object, and selecting one communication method from among the plurality of communication methods that can be selectively set in the wireless communication device; and setting, in the wireless communication device, control information used for communications based on the selected communication method.

Abstract: The present invention provides a system and a method, in which after authenticating a device, the user authentication methods are switched and used. Specifically, in performing user authentication via a terminal apparatus, the terminal apparatus is authenticated first and then based on this authentication result, a practical use of the terminal apparatus is determined, and the user authentication methods are switched so as to suit this practical use and the resultant method is implemented.

Abstract: According to one aspect of wireless communication control apparatus and method for a mobile object according to the present invention, the wireless communication apparatus and method include the steps of: collecting communication-state information corresponding to positional information of the mobile object for each of a plurality of communication methods that are used to make a connection to a wireless communication device of the mobile object, and that can be selectively set in the wireless communication device; referring to the communication-state information corresponding to the positional information indicating a current position of the mobile object, and selecting one communication method from among the plurality of communication methods that can be selectively set in the wireless communication device; and setting, in the wireless communication device, control information used for communications based on the selected communication method.

Abstract: An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: A multi-processor system includes a plurality of processor node control circuits in respective processor nodes, and a cache memory which is an external cache. Each of the processor node control circuits includes a summarized cache tag memory for storing “summarized information” which is information having a reduced number of bits by summarizing information on a cache tag portion in the cache memory and indicating whether each of blocks is effectively indexed in the cache tag portion. For cache coherence control, the summarized cache tag memory is first accessed, so that the cache tag portion is accessed only when it is determined that a target block is effectively indexed, to determine whether the cache coherence control for the node is required.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

Abstract: In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

Abstract: A clock distributing logic for distributing a clock signal in a circuit and reducing clock skew which occurs during the distributing of the clock signal in the circuit and a method for designing the same. The clock distributing logic includes at least two stages of clock amplifying gates for distributing the clock signal to source and sink sides of the circuit. Each of the at least two stages are successively connected to each other. Further, each of the at least two stages except a last stage includes clock amplifying gates of a same size providing a same driving ability. The last stage of clock amplifying gates includes clock amplifying gates of different sizes providing different driving abilities. The size of each clock amplifying gate of the last stage of clock amplifying gates is set to make the delay in distributing the clock signal in the circuit coincide with a desired clock signal distributing cycle.

Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract: A vector processor in which input/output of vector data to and from a vector register is effected by a load/store pipeline from a main memory, includes a load pipe for reading data of a plural-byte width from the main memory in one access, a plurality of vector registers for storing data read by the load pipe, each having a plurality of entries of an 8-byte width, mark bit stacks provided one for each of the vector registers and each having at least the same number of entries as those of the vector register, the entries of each mark bit stack storing mark bits for indicating which one of the plural-byte data stored in the entries of the corresponding vector register is valid, and a shifter for sending the valid data to an operation unit in accordance with the mark stored in the mark bit stack.

Abstract: Vector registers having logically equal address are arranged as two banks which can independently access ultra high speed RAM's. One bank holds all even-numbered elements of vector data and the other bank holds all odd-numbered elements of the vector data. A write address generator and a read address generator which are one half as fast as a clock rate of a machine cycle and which have a phase difference of one half period therebetween are provided so that the clock rate of the machine cycle may be set to one half of a total time of a write pitch and a read pitch of the vector registers.