Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract: In a vector processor in which a plurality of load/store pipelines from a plurality of arithmetic units and a main storage are used for input/output operations of vector data on a plurality of vector registers in a parallel fashion, vector data is communicated between the respective modules constituting a physically closed system. A sequence of odd-numbered vector data elements and a sequence of even-numbered vector data elements each having a phase difference of a half of a period of a basic machine cycle are communicated at a speed of the basic machine cycle. The module includes vector registers, each vector register is constituted with two RAM arrays being independently addressable and being capable of performing read and write operations at a speed which is twice the basic machine cycle.

Abstract: A built-in write control circuit of an IC memory receives first and second write enable signals that each have a duration equal to two operation cycles, the phase difference between these signals being equal to any odd number of operation cycles. The first and second write enable signals are converted into first and second write mode signals, respectively, each having a duration equal to one operation cycle, with the second write mode signal having a phase difference relative to the first write mode signal equal to the phase difference between the first and second write enable signals. A write pulse generator is included which receives a train of clock pulses having an interval equal to one operation cycle, and generates a train of write pulses in synchronism with the clock pulses. These write pulses are gated by each of the first and second write mode signals, and the resulting gated write signal is applied to sense amplifiers to control writing data into a memory array.