Patents by Inventor Masanaga Fukasawa

Masanaga Fukasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11798965
    Abstract: Provided is a solid-state imaging device capable of reducing bonding defects when two substrates are bonded to each other, and a method for manufacturing the solid-state imaging device. The solid-state imaging device includes a first substrate including a first electrode formed with a metal, and a second substrate that is a substrate bonded to the first substrate, the second substrate including a second electrode formed with a metal, the second electrode being bonded to the first electrode. In at least one of the first substrate or the second substrate, a diffusion preventing layer of the metal is formed for a layer formed with the metal filling a hole portion, the metal forming the electrodes.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 24, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masanaga Fukasawa
  • Publication number: 20220375763
    Abstract: Provided is an etching method that can ameliorate defects caused by etching during processing contact holes in a semiconductor device. The etching method includes attracting and adhering a first polymerization film onto an insulating film disposed on a semiconductor layer that contains silicon by plasma of a first gas, removing the first polymerization film by plasma of a second gas, and simultaneously, oxidizing an upper surface of the insulating film to form an alteration layer, attracting and adhering a second polymerization film onto the alteration layer by plasma of a third gas, and removing the second polymerization film and the alteration layer by plasma of a fourth gas.
    Type: Application
    Filed: June 15, 2020
    Publication date: November 24, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Akiko HIRATA, Masanaga FUKASAWA
  • Publication number: 20220122852
    Abstract: In an etching method for an oxide semiconductor film according to an embodiment of the present disclosure, a modified layer is formed in the oxide semiconductor film by using a first rare gas and the modified layer is sputtered by using a second rare gas different from the first rare gas.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 21, 2022
    Inventors: Akiko HIRATA, Tetsuya TATSUMI, Masanaga FUKASAWA, Satoshi HAMAGUCHI, Kazuhiro KARAHASHI
  • Publication number: 20210296384
    Abstract: To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device serving as an embodiment of the present disclosure includes: a storage element; a first contact that is electrically coupled to this storage element; a second contact that is positioned on an opposite side to the first contact in a first direction; a protective film that surrounds the storage element in a first plane orthogonal to the first direction; and a first hydrogen block layer that surrounds the protective film in the first plane. The second contact is electrically coupled to the storage element.
    Type: Application
    Filed: August 19, 2019
    Publication date: September 23, 2021
    Inventors: MASANAGA FUKASAWA, KAN SHIMIZU, TADAYUKI KIMURA, TOSHIAKI SHIRAIWA
  • Publication number: 20210249273
    Abstract: A first etching method of an oxide semiconductor film according to an embodiment of the present disclosure includes: forming a reduction layer in an oxide semiconductor film with use of a reducing gas; and sputtering the reduction layer with use of a rare gas.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 12, 2021
    Inventors: AKIKO HIRATA, MASANAGA FUKASAWA
  • Publication number: 20210167106
    Abstract: The present technology relates to a solid-state imaging device capable of reducing bonding defects when two substrates are bonded to each other, and a method for manufacturing the solid-state imaging device. The present technology provides a solid-state imaging device that includes: a first substrate including a first electrode formed with a metal; and a second substrate that is a substrate bonded to the first substrate, the second substrate including a second electrode formed with a metal, the second electrode being bonded to the first electrode. In at least one of the first substrate or the second substrate, a diffusion preventing layer of the metal is formed for a layer formed with the metal filling a hole portion, the metal forming the electrodes. The present technology can be applied to solid-state imaging devices, such as CMOS image sensors, for example.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 3, 2021
    Inventor: MASANAGA FUKASAWA
  • Patent number: 11017987
    Abstract: An etching method includes inputting, to a setting unit, at least electric power, a pressure, and a gas flow rate, performing etching processing in a chamber, on the basis of a value inputted to the setting unit, and calculating an ion energy distribution mathematical function, by using a measured value upon the etching processing.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 25, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masanaga Fukasawa
  • Publication number: 20200373135
    Abstract: An etching method includes inputting, to a setting unit, at least electric power, a pressure, and a gas flow rate, performing etching processing in a chamber, on the basis of a value inputted to the setting unit, and calculating an ion energy distribution mathematical function, by using a measured value upon the etching processing.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 26, 2020
    Inventor: MASANAGA FUKASAWA
  • Patent number: 10804313
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
  • Patent number: 10504839
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 10, 2019
    Assignee: Sony Corporation
    Inventor: Masanaga Fukasawa
  • Publication number: 20190080997
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Applicant: Sony Corporation
    Inventor: Masanaga Fukasawa
  • Patent number: 10157837
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: December 18, 2018
    Inventor: Masanaga Fukasawa
  • Publication number: 20180286911
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Applicant: Sony Corporation
    Inventors: Yoshihisa KAGAWA, Nobutoshi FUJII, Masanaga FUKASAWA, Tokihisa KANEGUCHI, Yoshiya HAGIMOTO, Kenichi AOYAGI, Ikue MITSUHASHI
  • Patent number: 10026769
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 17, 2018
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
  • Publication number: 20180076126
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Application
    Filed: November 16, 2017
    Publication date: March 15, 2018
    Inventor: Masanaga Fukasawa
  • Patent number: 9859214
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 2, 2018
    Assignee: Sony Corporation
    Inventor: Masanaga Fukasawa
  • Publication number: 20170207163
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Application
    Filed: March 30, 2017
    Publication date: July 20, 2017
    Inventor: Masanaga Fukasawa
  • Patent number: 9627359
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 18, 2017
    Assignee: Sony Corporation
    Inventor: Masanaga Fukasawa
  • Publication number: 20160307877
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventor: Masanaga Fukasawa
  • Patent number: 9425142
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: August 23, 2016
    Assignee: SONY CORPORATION
    Inventor: Masanaga Fukasawa