Patents by Inventor Masanaga Fukasawa
Masanaga Fukasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11798965Abstract: Provided is a solid-state imaging device capable of reducing bonding defects when two substrates are bonded to each other, and a method for manufacturing the solid-state imaging device. The solid-state imaging device includes a first substrate including a first electrode formed with a metal, and a second substrate that is a substrate bonded to the first substrate, the second substrate including a second electrode formed with a metal, the second electrode being bonded to the first electrode. In at least one of the first substrate or the second substrate, a diffusion preventing layer of the metal is formed for a layer formed with the metal filling a hole portion, the metal forming the electrodes.Type: GrantFiled: December 6, 2018Date of Patent: October 24, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Masanaga Fukasawa
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Publication number: 20220375763Abstract: Provided is an etching method that can ameliorate defects caused by etching during processing contact holes in a semiconductor device. The etching method includes attracting and adhering a first polymerization film onto an insulating film disposed on a semiconductor layer that contains silicon by plasma of a first gas, removing the first polymerization film by plasma of a second gas, and simultaneously, oxidizing an upper surface of the insulating film to form an alteration layer, attracting and adhering a second polymerization film onto the alteration layer by plasma of a third gas, and removing the second polymerization film and the alteration layer by plasma of a fourth gas.Type: ApplicationFiled: June 15, 2020Publication date: November 24, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Akiko HIRATA, Masanaga FUKASAWA
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Publication number: 20220122852Abstract: In an etching method for an oxide semiconductor film according to an embodiment of the present disclosure, a modified layer is formed in the oxide semiconductor film by using a first rare gas and the modified layer is sputtered by using a second rare gas different from the first rare gas.Type: ApplicationFiled: December 19, 2019Publication date: April 21, 2022Inventors: Akiko HIRATA, Tetsuya TATSUMI, Masanaga FUKASAWA, Satoshi HAMAGUCHI, Kazuhiro KARAHASHI
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Publication number: 20210296384Abstract: To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device serving as an embodiment of the present disclosure includes: a storage element; a first contact that is electrically coupled to this storage element; a second contact that is positioned on an opposite side to the first contact in a first direction; a protective film that surrounds the storage element in a first plane orthogonal to the first direction; and a first hydrogen block layer that surrounds the protective film in the first plane. The second contact is electrically coupled to the storage element.Type: ApplicationFiled: August 19, 2019Publication date: September 23, 2021Inventors: MASANAGA FUKASAWA, KAN SHIMIZU, TADAYUKI KIMURA, TOSHIAKI SHIRAIWA
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Publication number: 20210249273Abstract: A first etching method of an oxide semiconductor film according to an embodiment of the present disclosure includes: forming a reduction layer in an oxide semiconductor film with use of a reducing gas; and sputtering the reduction layer with use of a rare gas.Type: ApplicationFiled: April 10, 2019Publication date: August 12, 2021Inventors: AKIKO HIRATA, MASANAGA FUKASAWA
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Publication number: 20210167106Abstract: The present technology relates to a solid-state imaging device capable of reducing bonding defects when two substrates are bonded to each other, and a method for manufacturing the solid-state imaging device. The present technology provides a solid-state imaging device that includes: a first substrate including a first electrode formed with a metal; and a second substrate that is a substrate bonded to the first substrate, the second substrate including a second electrode formed with a metal, the second electrode being bonded to the first electrode. In at least one of the first substrate or the second substrate, a diffusion preventing layer of the metal is formed for a layer formed with the metal filling a hole portion, the metal forming the electrodes. The present technology can be applied to solid-state imaging devices, such as CMOS image sensors, for example.Type: ApplicationFiled: December 6, 2018Publication date: June 3, 2021Inventor: MASANAGA FUKASAWA
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Patent number: 11017987Abstract: An etching method includes inputting, to a setting unit, at least electric power, a pressure, and a gas flow rate, performing etching processing in a chamber, on the basis of a value inputted to the setting unit, and calculating an ion energy distribution mathematical function, by using a measured value upon the etching processing.Type: GrantFiled: July 3, 2018Date of Patent: May 25, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Masanaga Fukasawa
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Publication number: 20200373135Abstract: An etching method includes inputting, to a setting unit, at least electric power, a pressure, and a gas flow rate, performing etching processing in a chamber, on the basis of a value inputted to the setting unit, and calculating an ion energy distribution mathematical function, by using a measured value upon the etching processing.Type: ApplicationFiled: July 3, 2018Publication date: November 26, 2020Inventor: MASANAGA FUKASAWA
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Patent number: 10804313Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: GrantFiled: June 6, 2018Date of Patent: October 13, 2020Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
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Patent number: 10504839Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: GrantFiled: November 13, 2018Date of Patent: December 10, 2019Assignee: Sony CorporationInventor: Masanaga Fukasawa
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Publication number: 20190080997Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Applicant: Sony CorporationInventor: Masanaga Fukasawa
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Patent number: 10157837Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: GrantFiled: November 16, 2017Date of Patent: December 18, 2018Inventor: Masanaga Fukasawa
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Publication number: 20180286911Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: ApplicationFiled: June 6, 2018Publication date: October 4, 2018Applicant: Sony CorporationInventors: Yoshihisa KAGAWA, Nobutoshi FUJII, Masanaga FUKASAWA, Tokihisa KANEGUCHI, Yoshiya HAGIMOTO, Kenichi AOYAGI, Ikue MITSUHASHI
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Patent number: 10026769Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: GrantFiled: September 19, 2014Date of Patent: July 17, 2018Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
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Publication number: 20180076126Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: ApplicationFiled: November 16, 2017Publication date: March 15, 2018Inventor: Masanaga Fukasawa
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Patent number: 9859214Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: GrantFiled: March 30, 2017Date of Patent: January 2, 2018Assignee: Sony CorporationInventor: Masanaga Fukasawa
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Publication number: 20170207163Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: ApplicationFiled: March 30, 2017Publication date: July 20, 2017Inventor: Masanaga Fukasawa
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Patent number: 9627359Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: GrantFiled: June 27, 2016Date of Patent: April 18, 2017Assignee: Sony CorporationInventor: Masanaga Fukasawa
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Publication number: 20160307877Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventor: Masanaga Fukasawa
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Patent number: 9425142Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.Type: GrantFiled: August 20, 2015Date of Patent: August 23, 2016Assignee: SONY CORPORATIONInventor: Masanaga Fukasawa