Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.

Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.

Abstract: The simulation method is for predicting a damage amount due to ultraviolet rays in manufacturing a semiconductor device.

Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.

Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.

Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.

Abstract: An arrangement of semiconductor chips is provided. The arrangement includes a plurality of stacked semiconductor chips each including an integrated circuit. At least one via is formed through the thickness of at least one of the semiconductor chips. A carbon nanotube conductor is formed in the via. The conductor has first and second opposite ends. The first end of the conductor is selectively interconnected with the integrated circuit of its semiconductor chip and the second end of the conductor is selectively interconnected with the integrated circuit of another of the semiconductor chips.

Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device, including the step of ashing away by a plasma treatment an organic material film formed over a substrate with an inter-layer insulator film therebetween, wherein the plasma treatment is conducted while electric power applied so as to draw ions in a plasma toward the substrate is periodically turned ON and OFF.

Abstract: A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening. The capping layer and the dielectric layer are etched through the resist pattern to form the first interconnect opening. The resist pattern is removed and a barrier layer is applied over the capping layer and in the first interconnect opening. An interconnection is formed by filling the first interconnect opening with conductive material. The interconnection is planarized to remove excess material and a portion of the first dielectric layer damaged by the planarizing step is selectively etched. A second dielectric layer is applied to replace the damaged portion of the first dielectric.

Abstract: A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening. The capping layer and the dielectric layer are etched through the resist pattern to form the first interconnect opening. The resist pattern is removed and a barrier layer is applied over the capping layer and in the first interconnect opening. An interconnection is formed by filling the first interconnect opening with conductive material. The interconnection is planarized to remove excess material and a portion of the first dielectric layer damaged by the planarizing step is selectively etched. A second dielectric layer is applied to replace the damaged portion of the first dielectric.

Abstract: A method of fabricating a damascene interconnection is provided. The method begins by forming on a substrate a low k dielectric layer and a resist pattern over the low k dielectric layer to define a first interconnect opening. The low k dielectric layer is etched through the resist pattern to form the first interconnect opening, whereby damage arises to a portion of the low k dielectric layer defining a sidewall of the first interconnect opening. The resist pattern is then removed and a barrier layer is applied to line the first interconnect opening. An interconnection is formed by filling the first interconnect opening with a conductive material. The interconnection is planarized to remove excess material, whereby an underlying portion of the low k dielectric layer is damaged during planarizing. The damaged underlying portion of the low k dielectric layer and the damaged sidewall portion of the low k dielectric layer are both repaired at least in part after performing the planarizing step.

Abstract: A semiconductor device is provided that includes a substrate, a lower dielectric layer located on a substrate, and at least one lower conductive interconnect located in the lower dielectric layer. A cap layer is located over the lower conductive interconnect and at least a first dielectric layer is located on the cap layer. At least a first trench/via is formed through the first dielectric layer and the cap layer and is at least in part located over a portion of the lower conductive interconnect. The portion of the lower conductive interconnect defines a chamfered shoulder. A barrier layer lines the first trench/via. A conductive material fills the first trench/via and also fills a region of the lower dielectric layer adjacent the chamfered shoulder of the lower conductive interconnect.

Abstract: An arrangement of semiconductor chips is provided. The arrangement includes a plurality of stacked semiconductor chips each including an integrated circuit. At least one via is formed through the thickness of at least one of the semiconductor chips. A carbon nanotube conductor is formed in the via. The conductor has first and second opposite ends. The first end of the conductor is selectively interconnected with the integrated circuit of its semiconductor chip and the second end of the conductor is selectively interconnected with the integrated circuit of another of the semiconductor chips.

Abstract: A method of rapid etching of an insulating film including an organic-based dielectric film without forming a damage layer or causing decline of the throughput, including the steps of forming an insulating film including an organic-based dielectric film such as a stacked film comprised of a polyarylether film or other organic-based dielectric film and a silicon oxide-based dielectric film or other insulating film, forming a mask layer by patterning above the insulating film, and when etching the organic-based dielectric film portion, using ions or radicals containing NH group generated by gaseous discharge in a mixed gas of hydrogen gas and nitrogen gas or a mixed gas of ammonia gas for etching using the mask layer as an etching mask, to etch the insulating layer and form openings etc. while generating reaction products containing CN group.

Abstract: A method of rapid etching of an insulating film including an organic-based dielectric film without forming a damage layer or causing decline of the throughput, including the steps of forming an insulating film including an organic-based dielectric film such as a stacked film comprised of a polyarylether film or other organic-based dielectric film and a silicon oxide-based dielectric film or other insulating film, forming a mask layer by patterning above the insulating film, and when etching the organic-based dielectric film portion, using ions or radicals containing NH group generated by gaseous discharge in a mixed gas of hydrogen gas and nitrogen gas or a mixed gas of ammonia gas for etching using the mask layer as an etching mask, to etch the insulating layer and form openings etc. while generating reaction products containing CN group.

Abstract: A method of rapid etching of an insulating film including an organic-based dielectric film without forming a damage layer or causing decline of the throughput, including the steps of forming an insulating film including an organic-based dielectric film such as a stacked film having a polyarylether film or other organic-based dielectric film and a silicon oxide-based dielectric film or other insulating film, forming a mask layer by patterning above the insulating film, and when etching the organic-based dielectric film portion, using ions or radicals containing NH group generated by gaseous discharge in a mixed gas of hydrogen gas and nitrogen gas or a mixed gas of ammonia gas for etching using the mask layer as an etching mask, to etch the insulating layer and form openings etc. while generating reaction products containing CN group.

Abstract: A stacked insulating film having an organic insulating film, and a carbon-containing silicon oxide film formed on the organic insulating film is disclosed. The carbon-containing silicon oxide film has a carbon content of 8 atom % to 25 atom %.