Patents by Inventor Masanao Yamaoka

Masanao Yamaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11656787
    Abstract: A calculation system includes a variable memory storing a value indicating a state of a variable of a mixed integer quadratic programming problem; a state transition calculation block that calculates the next state of the value indicating the state of the variable; a nonlinear coefficient memory that stores a nonlinear coefficient of the state transition calculation block; a linear coefficient memory that stores a linear coefficient of the state transition calculation block; a weight input line that receives a weight signal of the state transition calculation block; and a temperature input line that receives a temperature signal of the state transition calculation block. The state transition calculation block includes a difference calculation block that calculates a difference calculation by using the weight signal, the nonlinear coefficient, and the linear coefficient. A next state determination block calculates the next state of the variable using the value read from the variable memory.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 23, 2023
    Assignee: HITACHI, LTD.
    Inventors: Takuya Okuyama, Masanao Yamaoka
  • Publication number: 20220343202
    Abstract: An arithmetic circuit includes: a spin memory that stores a value indicating a state of one spin in an interaction model; an interaction coefficient auxiliary memory that stores an interaction coefficient of a subfunction corresponding to the spin memory; an external magnetic field coefficient auxiliary memory that stores an external magnetic field coefficient of the subfunction corresponding to the spin memory; a weight input line that receives a weight signal of the subfunction; an interaction coefficient calculation unit that calculates a weighted subfunction interaction coefficient by using the weight signal of the subfunction and the interaction coefficient of the subfunction; an external magnetic field coefficient calculation unit that calculates a weighted subfunction external magnetic field coefficient; and a next state calculation unit that calculates a next state of the spin based on the value of the spin, the weighted subfunction interaction coefficient, and the weighted subfunction external magnet
    Type: Application
    Filed: October 29, 2019
    Publication date: October 27, 2022
    Inventors: Takuya OKUYAMA, Masanao YAMAOKA
  • Publication number: 20220308837
    Abstract: Provided is an optimization method including executing a ground state search for an interaction model by a ground state search in a surrogate interaction model including D (D is a natural number of three or more) variable groups each having N continuous variables by using an information processing apparatus, the interaction model having a third-order or higher-order energy function including N (N is a natural number) continuous variables and discrete variables. The ground state search is executed based on simulated annealing. An interaction relation of the surrogate interaction model has a complete D-part graph structure. A coupling is set between i-th variable pairs in the respective variable groups of the surrogate interaction model. The information processing apparatus is operated to simultaneously update all variables of one variable group from among the D variable groups when performing a state transition in the surrogate interaction model.
    Type: Application
    Filed: August 11, 2021
    Publication date: September 29, 2022
    Inventors: Yusuke SUGITA, Takuya OKUYAMA, Masanao YAMAOKA
  • Patent number: 11443217
    Abstract: It is possible to perform a stochastic process based on a metropolis algorithm while reducing a physical quantity of a circuit. Provided is an information processing apparatus including one or a plurality of array circuits. In this apparatus, each of the array circuits includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of one node of a coupling model, a second memory that stores a coupling coefficient indicating coupling from a node of another unit connected to an unit of the second memory, and a logic circuit that determines a value indicating a subsequent state of the one node based on a value indicating a state of the node of the other unit and the coupling coefficient. Further, the logic circuit sets a first random variable in accordance with an exponential distribution of a parameter ? as an input.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 13, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Okuyama, Masato Hayashi, Masanao Yamaoka
  • Publication number: 20220230252
    Abstract: [Problem] To efficiently generate multiple portfolio candidates based on investment policies of each financial institution and present the portfolio candidates to a user in an easily understandable form. [Solution] A portfolio creation assistance device 100, includes: a storage unit 101 storing information on each of financial commodities; and a computation unit 104 performing a computation of an Ising model of a predetermined expression in which items of an expected return rate, a price drop risk, and a market sensitivity in a portfolio including combined predetermined ones of the financial commodities indicated by the information are combined with weights for the respective items, wherein the computation unit 104 outputs portfolios each obtained for one of patterns of the weights for the respective items as a result of the computation to a predetermined device, the portfolios each minimizing a value of the predetermined expression.
    Type: Application
    Filed: April 24, 2020
    Publication date: July 21, 2022
    Applicant: HITACHI, LTD.
    Inventors: Manabu SUGANUMA, Jun OGAWA, Masanao YAMAOKA, Takuya OKUYAMA
  • Publication number: 20220129780
    Abstract: Searching for a ground state of an Ising model is performed so that a combinatorial optimization problem is efficiently solved. An information processing apparatus stores an energy function setting an interaction between an i-th spin of a first spin group and a j-th spin of a second spin group so that the i-th spin of the first spin group and the j-th spin of the second spin group have the same value in a ground state in an interaction relationship of an Ising model represented as a complete bipartite graph connecting N spins of the first spin group and of the second spin group, and searches for the ground state of the Ising model based on the energy function and information unique to the spins. The search for the ground state of the Ising model is performed by applying an algorithm of simulated annealing method to the above-mentioned energy function.
    Type: Application
    Filed: March 29, 2019
    Publication date: April 28, 2022
    Inventors: Takuya OKUYAMA, Masanao YAMAOKA
  • Publication number: 20220101099
    Abstract: According to one embodiment, provided is an information processing system including a parent device and a plurality of child devices. The child device constitutes at least a portion of at least one device selected from a function approximator and an annealing machine, each of the parent devices and the plurality of child devices include a communication interface, and the communication interface is at least one selected from a wireless communication interface and a wired communication interface including an analog circuit. Data to be processed by the child device is transmitted from the parent device to at least one of the plurality of child devices, and an output of at least one node of the child device is transmitted to at least one of the parent device and the other child devices.
    Type: Application
    Filed: June 1, 2021
    Publication date: March 31, 2022
    Applicant: HITACHI, LTD.
    Inventors: Takashi OSHIMA, Norikatsu TAKAURA, Masanao YAMAOKA, Yoshitaka SASAGO
  • Publication number: 20220027082
    Abstract: A calculation system includes a variable memory storing a value indicating a state of a variable of a mixed integer quadratic programming problem; a state transition calculation block that calculates the next state of the value indicating the state of the variable; a nonlinear coefficient memory that stores a nonlinear coefficient of the state transition calculation block; a linear coefficient memory that stores a linear coefficient of the state transition calculation block; a weight input line that receives a weight signal of the state transition calculation block; and a temperature input line that receives a temperature signal of the state transition calculation block. The state transition calculation block includes a difference calculation block that calculates a difference calculation by using the weight signal, the nonlinear coefficient, and the linear coefficient. A next state determination block calculates the next state of the variable using the value read from the variable memory.
    Type: Application
    Filed: April 29, 2020
    Publication date: January 27, 2022
    Inventors: Takuya OKUYAMA, Masanao YAMAOKA
  • Publication number: 20210398156
    Abstract: An information providing device 100 is configured to include a storage unit 101 that stores price information 125 on various financial products, and a calculation unit 104 that performs calculation on an Ising model in which a price increase-decrease event of each financial product on an estimated price determined based on an actual price of the financial product indicated in the price information and a sensitivity of the financial product to another financial product is set as a spin, and in which sensitivities between prices of the financial products are set as the strengths of interactions between the spins, wherein the calculation unit outputs, to a specified device, information on a future price of at least one financial product of the financial products based on a result of the calculation.
    Type: Application
    Filed: October 25, 2019
    Publication date: December 23, 2021
    Applicant: HITACHI, LTD.
    Inventors: Jun OGAWA, Yukiyo KIMURA, Takuya OKUYAMA, Masanao YAMAOKA
  • Patent number: 10896241
    Abstract: An information processing apparatus manufactured at low cost and with ease and that is capable of making a search for a ground state of an arbitrary Ising model. An information processing unit containing a plurality of semiconductor chips, each retains a value of one spin or values of a plurality of spins and simulates interactions among the spins, inter-chip wiring between the necessary semiconductor chips, and a control unit that cause each semiconductor chip to perform interaction computation. The control unit converts data of a problem into data of a lattice-shaped Ising model, which is possibly expressed by the plurality of semiconductor chips, without causing a spin arrangement, in a ground state of an Ising model for the problem, to be changed. The data of the lattice-shaped Ising model is divided for allocation to the plurality of semiconductor chips, and causes each semiconductor chip to perform the interaction computation.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 19, 2021
    Assignee: HITACHI, LTD.
    Inventors: Takuya Okuyama, Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Akihito Akai
  • Patent number: 10839044
    Abstract: Hardware for speeding up MCMC is realized. An information processing apparatus includes a plurality of Ising chips and a controller that controls the plurality of Ising chips. Each of the plurality of Ising chips includes a plurality of units, and each of the plurality of units retains a spin state. The controller instructs one set of Ising chips among the plurality of Ising chips to compare values of spin states of corresponding units and instructs the one set of Ising chip to invert values of a portion of spins among spins having different values of spin states of the corresponding units.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 17, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takuya Okuyama, Masanao Yamaoka
  • Patent number: 10795404
    Abstract: An aspect of the present invention for solving the above problem is a system including a first computer, a control module controlled by the first computer, and a second computer configured to be associated with the control module. The second computer includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit. The arithmetic circuit performs an arithmetic process of determining a value indicating a state of a node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory. The control module supplies a control signal for controlling the arithmetic process to the second computer.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: October 6, 2020
    Assignee: HITACHI, LTD.
    Inventors: Masanao Yamaoka, Takeshi Kato, Chihiro Yoshimura, Masato Hayashi
  • Patent number: 10783184
    Abstract: A computer includes a data generation unit and a storage unit which retains graph information for managing a graph configured from a plurality of vertexes and sides. The data generation unit performs acquiring a plurality of data and graph information and assuring storage regions in number equal to the number of vertexes, converting each data into an input value and setting at least one input value to a storage region corresponding to at least one vertex, executing an updating process for updating a value set to a storage region corresponding to a first vertex using the value set to the storage region corresponding to the first vertex and a value set to a storage region corresponding to a different vertex directly connected to the first vertex, and outputting a set of values set to the storage regions corresponding to the vertexes as the feature value.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 22, 2020
    Assignee: HITACHI, LTD.
    Inventors: Junichi Miyakoshi, Masanao Yamaoka, Hiromasa Takahashi, Shirun Ho, Kenzo Kurotsuchi, Sanato Nagata
  • Patent number: 10665280
    Abstract: The information processing apparatus is provided with a plurality of spin units for storing spin states and searching for a predetermined state by updating a spin state of a spin unit based on spin states of other spin units. The information processing apparatus includes: a first semiconductor integrated circuit device in which a plurality of first spin units are formed; a second semiconductor integrated circuit device in which a second spin unit is formed; an inter-chip wire connecting the first semiconductor integrated circuit device and the second semiconductor integrated circuit device; and a transmitter connection unit connected to the inter-chip wire and simultaneously shared by the plurality of first spin units. The transmitter connection unit transmits a spin state of a spin unit of which the spin state is changed among the plurality of first spin units, to the second semiconductor integrated circuit device through the inter-chip wire.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: May 26, 2020
    Assignee: HITACHI, LTD.
    Inventors: Masato Hayashi, Masanao Yamaoka
  • Patent number: 10573376
    Abstract: A logic circuit in a system LSI (Large Scale Integrated Circuit) is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM (Static Random Access Memory) circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 25, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 10452721
    Abstract: An autopoietic information processing system which is an information processing system for collecting and outputting information includes: a means that inputs first information; a means that collects second information related to the first information; a means that selects third information from the second information; a means that outputs second or third information; a means that collects the second information by setting the third information as new first information; a means that merges the existing second information and new second information at a predetermined rate; a means that selects new third information from the merged second information; and a means that outputs the merged second information or the new third information. The means are recursively operated to continuously provide new information which leads to awareness and discovery of a user.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: October 22, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Kato, Hiroyuki Mizuno, Yasuyuki Kudo, Masanao Yamaoka, Junichi Miyakoshi, Kouji Fukuda, Yasuhiro Asa
  • Patent number: 10446224
    Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
  • Publication number: 20190267065
    Abstract: The information processing apparatus is provided with a plurality of spin units for storing spin states and searching for a predetermined state by updating a spin state of a spin unit based on spin states of other spin units. The information processing apparatus includes: a first semiconductor integrated circuit device in which a plurality of first spin units are formed; a second semiconductor integrated circuit device in which a second spin unit is formed; an inter-chip wire connecting the first semiconductor integrated circuit device and the second semiconductor integrated circuit device; and a transmitter connection unit connected to the inter-chip wire and simultaneously shared by the plurality of first spin units. The transmitter connection unit transmits a spin state of a spin unit of which the spin state is changed among the plurality of first spin units, to the second semiconductor integrated circuit device through the inter-chip wire.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 29, 2019
    Inventors: Masato HAYASHI, Masanao YAMAOKA
  • Patent number: 10366745
    Abstract: Provided are a semiconductor device and an information processing device that can be manufactured easily at low cost and can calculate an arbitrary interaction model such as an Ising model. A semiconductor device that performs a non-linear operation includes a memory, a reading unit that reads data from the memory, a majority circuit that inputs a result of a predetermined operation on the data read by the reading unit, and a write circuit that receives an output of the majority circuit, a value of a predetermined signal is stochastically inverted at a preceding stage of the majority circuit.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: July 30, 2019
    Assignee: HITACHI, LTD.
    Inventors: Takuya Okuyama, Masanao Yamaoka
  • Publication number: 20190172528
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada