Patents by Inventor Masanao Yamaoka

Masanao Yamaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896241
    Abstract: An information processing apparatus manufactured at low cost and with ease and that is capable of making a search for a ground state of an arbitrary Ising model. An information processing unit containing a plurality of semiconductor chips, each retains a value of one spin or values of a plurality of spins and simulates interactions among the spins, inter-chip wiring between the necessary semiconductor chips, and a control unit that cause each semiconductor chip to perform interaction computation. The control unit converts data of a problem into data of a lattice-shaped Ising model, which is possibly expressed by the plurality of semiconductor chips, without causing a spin arrangement, in a ground state of an Ising model for the problem, to be changed. The data of the lattice-shaped Ising model is divided for allocation to the plurality of semiconductor chips, and causes each semiconductor chip to perform the interaction computation.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 19, 2021
    Assignee: HITACHI, LTD.
    Inventors: Takuya Okuyama, Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Akihito Akai
  • Patent number: 10839044
    Abstract: Hardware for speeding up MCMC is realized. An information processing apparatus includes a plurality of Ising chips and a controller that controls the plurality of Ising chips. Each of the plurality of Ising chips includes a plurality of units, and each of the plurality of units retains a spin state. The controller instructs one set of Ising chips among the plurality of Ising chips to compare values of spin states of corresponding units and instructs the one set of Ising chip to invert values of a portion of spins among spins having different values of spin states of the corresponding units.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 17, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takuya Okuyama, Masanao Yamaoka
  • Patent number: 10795404
    Abstract: An aspect of the present invention for solving the above problem is a system including a first computer, a control module controlled by the first computer, and a second computer configured to be associated with the control module. The second computer includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit. The arithmetic circuit performs an arithmetic process of determining a value indicating a state of a node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory. The control module supplies a control signal for controlling the arithmetic process to the second computer.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: October 6, 2020
    Assignee: HITACHI, LTD.
    Inventors: Masanao Yamaoka, Takeshi Kato, Chihiro Yoshimura, Masato Hayashi
  • Patent number: 10783184
    Abstract: A computer includes a data generation unit and a storage unit which retains graph information for managing a graph configured from a plurality of vertexes and sides. The data generation unit performs acquiring a plurality of data and graph information and assuring storage regions in number equal to the number of vertexes, converting each data into an input value and setting at least one input value to a storage region corresponding to at least one vertex, executing an updating process for updating a value set to a storage region corresponding to a first vertex using the value set to the storage region corresponding to the first vertex and a value set to a storage region corresponding to a different vertex directly connected to the first vertex, and outputting a set of values set to the storage regions corresponding to the vertexes as the feature value.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 22, 2020
    Assignee: HITACHI, LTD.
    Inventors: Junichi Miyakoshi, Masanao Yamaoka, Hiromasa Takahashi, Shirun Ho, Kenzo Kurotsuchi, Sanato Nagata
  • Patent number: 10665280
    Abstract: The information processing apparatus is provided with a plurality of spin units for storing spin states and searching for a predetermined state by updating a spin state of a spin unit based on spin states of other spin units. The information processing apparatus includes: a first semiconductor integrated circuit device in which a plurality of first spin units are formed; a second semiconductor integrated circuit device in which a second spin unit is formed; an inter-chip wire connecting the first semiconductor integrated circuit device and the second semiconductor integrated circuit device; and a transmitter connection unit connected to the inter-chip wire and simultaneously shared by the plurality of first spin units. The transmitter connection unit transmits a spin state of a spin unit of which the spin state is changed among the plurality of first spin units, to the second semiconductor integrated circuit device through the inter-chip wire.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: May 26, 2020
    Assignee: HITACHI, LTD.
    Inventors: Masato Hayashi, Masanao Yamaoka
  • Patent number: 10573376
    Abstract: A logic circuit in a system LSI (Large Scale Integrated Circuit) is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM (Static Random Access Memory) circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 25, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 10452721
    Abstract: An autopoietic information processing system which is an information processing system for collecting and outputting information includes: a means that inputs first information; a means that collects second information related to the first information; a means that selects third information from the second information; a means that outputs second or third information; a means that collects the second information by setting the third information as new first information; a means that merges the existing second information and new second information at a predetermined rate; a means that selects new third information from the merged second information; and a means that outputs the merged second information or the new third information. The means are recursively operated to continuously provide new information which leads to awareness and discovery of a user.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: October 22, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Kato, Hiroyuki Mizuno, Yasuyuki Kudo, Masanao Yamaoka, Junichi Miyakoshi, Kouji Fukuda, Yasuhiro Asa
  • Patent number: 10446224
    Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
  • Publication number: 20190267065
    Abstract: The information processing apparatus is provided with a plurality of spin units for storing spin states and searching for a predetermined state by updating a spin state of a spin unit based on spin states of other spin units. The information processing apparatus includes: a first semiconductor integrated circuit device in which a plurality of first spin units are formed; a second semiconductor integrated circuit device in which a second spin unit is formed; an inter-chip wire connecting the first semiconductor integrated circuit device and the second semiconductor integrated circuit device; and a transmitter connection unit connected to the inter-chip wire and simultaneously shared by the plurality of first spin units. The transmitter connection unit transmits a spin state of a spin unit of which the spin state is changed among the plurality of first spin units, to the second semiconductor integrated circuit device through the inter-chip wire.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 29, 2019
    Inventors: Masato HAYASHI, Masanao YAMAOKA
  • Patent number: 10366745
    Abstract: Provided are a semiconductor device and an information processing device that can be manufactured easily at low cost and can calculate an arbitrary interaction model such as an Ising model. A semiconductor device that performs a non-linear operation includes a memory, a reading unit that reads data from the memory, a majority circuit that inputs a result of a predetermined operation on the data read by the reading unit, and a write circuit that receives an output of the majority circuit, a value of a predetermined signal is stochastically inverted at a preceding stage of the majority circuit.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: July 30, 2019
    Assignee: HITACHI, LTD.
    Inventors: Takuya Okuyama, Masanao Yamaoka
  • Publication number: 20190172528
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 10304526
    Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
  • Publication number: 20190155330
    Abstract: An aspect of the present invention for solving the above problem is a system including a first computer, a control module controlled by the first computer, and a second computer configured to be associated with the control module. The second computer includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit. The arithmetic circuit performs an arithmetic process of determining a value indicating a state of a node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory. The control module supplies a control signal for controlling the arithmetic process to the second computer.
    Type: Application
    Filed: August 24, 2015
    Publication date: May 23, 2019
    Inventors: Masanao YAMAOKA, Takeshi KATO, Chihiro YOSHIMURA, Masato HAYASHI
  • Publication number: 20190130295
    Abstract: It is possible to perform a stochastic process based on a metropolis algorithm while reducing a physical quantity of a circuit. Provided is an information processing apparatus including one or a plurality of array circuits. In this apparatus, each of the array circuits includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of one node of a coupling model, a second memory that stores a coupling coefficient indicating coupling from a node of another unit connected to an unit of the second memory, and a logic circuit that determines a value indicating a subsequent state of the one node based on a value indicating a state of the node of the other unit and the coupling coefficient. Further, the logic circuit sets a first random variable in accordance with an exponential distribution of a parameter ? as an input.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 2, 2019
    Inventors: Takuya Okuyama, Masato Hayashi, Masanao Yamaoka
  • Patent number: 10229732
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Grant
    Filed: January 20, 2018
    Date of Patent: March 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 10191880
    Abstract: A semiconductor device in which a ground state of an Ising model is realized, includes a spin array in which a spin unit is formed, the spin unit including a memory cell storing a value of one spin in an Ising model, a memory cell storing an interaction coefficient from an adjacent spin interacting with the spin, a memory cell storing an external magnetic field coefficient of the spin, and a circuit deciding a next state of the spin by binary majority decision logic based on a product of the value of each of the adjacent spins and the corresponding interaction coefficient, and the external magnetic field coefficient. The spin array is formed by having a plurality of the spin units, each having each spin allocated thereto, arranged and connected on a two-dimensional plane on a semiconductor substrate in the state where a topology of the Ising model is maintained.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: January 29, 2019
    Assignee: HITACHI, LTD.
    Inventors: Chihiro Yoshimura, Masanao Yamaoka
  • Publication number: 20180349325
    Abstract: Hardware for speeding up MCMC is realized. An information processing apparatus includes a plurality of Ising chips and a controller that controls the plurality of Ising chips. Each of the plurality of Ising chips includes a plurality of units, and each of the plurality of units retains a spin state. The controller instructs one set of Ising chips among the plurality of Ising chips to compare values of spin states of corresponding units and instructs the one set of Ising chip to invert values of a portion of spins among spins having different values of spin states of the corresponding units.
    Type: Application
    Filed: February 28, 2018
    Publication date: December 6, 2018
    Inventors: Takuya Okuyama, Masanao Yamaoka
  • Publication number: 20180350430
    Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
    Type: Application
    Filed: August 9, 2018
    Publication date: December 6, 2018
    Inventors: Shigenobu KOMATSU, Masanao YAMAOKA, Noriaki MAEDA, Masao MORIMOTO, Yasuhisa SHIMAZAKI, Yasuyuki OKUMA, Toshiaki SANO
  • Publication number: 20180300287
    Abstract: An information processing apparatus manufactured at low cost and with ease and that is capable of making a search for a ground state of an arbitrary Ising model. An information processing unit containing a plurality of semiconductor chips, each retains a value of one spin or values of a plurality of spins and simulates interactions among the spins, inter-chip wiring between the necessary semiconductor chips, and a control unit that cause each semiconductor chip to perform interaction computation. The control unit converts data of a problem into data of a lattice-shaped Ising model, which is possibly expressed by the plurality of semiconductor chips, without causing a spin arrangement, in a ground state of an Ising model for the problem, to be changed. The data of the lattice-shaped Ising model is divided for allocation to the plurality of semiconductor chips, and causes each semiconductor chip to perform the interaction computation.
    Type: Application
    Filed: June 9, 2015
    Publication date: October 18, 2018
    Applicant: HITACHI, LTD.
    Inventors: Takuya OKUYAMA, Masanao YAMAOKA, Chihiro YOSHIMURA, Masato HAYASHI, Akihito AKAI
  • Patent number: 10102180
    Abstract: An object of the invention is to provide a majority circuit which may be manufactured cheaply and easily and may process necessary majority functions for calculation in an interaction model. The majority circuit according to the invention simplifies the processing of the majority function by using a bitonic sort circuit to round the sum of input signals to a power of 2.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 16, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Okuyama, Masanao Yamaoka