Abstract: A computer includes a data generation unit and a storage unit which retains graph information for managing a graph configured from a plurality of vertexes and sides. The data generation unit performs acquiring a plurality of data and graph information and assuring storage regions in number equal to the number of vertexes, converting each data into an input value and setting at least one input value to a storage region corresponding to at least one vertex, executing an updating process for updating a value set to a storage region corresponding to a first vertex using the value set to the storage region corresponding to the first vertex and a value set to a storage region corresponding to a different vertex directly connected to the first vertex, and outputting a set of values set to the storage regions corresponding to the vertexes as the feature value.

Abstract: In a semiconductor device in which components to be a basic configuration unit are arranged in an array shape for calculating an interaction model, a technique capable of changing a topology between the components is provided. A semiconductor device includes a plurality of units each of which includes a first memory cell for storing a value indicating a state of one node of an interaction model, a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node, and a calculation circuit for determining a value indicating a next state of the one node based on a value indicating a state of the connected node and on the interaction coefficient. In addition, the semiconductor device includes a plurality of switches for connecting or disconnecting the plurality of units to/from each other.

Abstract: A highly-convenient information processing system capable of obtaining a solution of a problem under conditions desired by a user and a management apparatus capable of enhancing the convenience of the information processing system are suggested.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: An object is to continuously provide new information which leads to awareness and discovery of a user. An autopoietic information processing system which is an information processing system for collecting and outputting information includes: a means that inputs first information; a means that collects second information related to the first information; a means that selects third information from the second information; a means that outputs second or third information; a means that collects the second information by setting the third information as new first information; a means that merges the existing second information and new second information at a predetermined rate; a means that selects new third information from the merged second information; and a means that outputs the merged second information or the new third information. The means are recursively operated.

Abstract: A semiconductor integrated circuit apparatus 23 is used for obtaining an optimum solution using an Ising model, and the semiconductor integrated circuit apparatus 23 includes plural spin cells 1 that are connected with each other. Here, each spin cell 1 includes: a memory cell 9(N) for memorizing a spin value; a computing circuit 10 for computing interactions among the plural spin cells that are connected with each other; a memory circuit 4 for holding at least one-bit data; and an inversion logic circuit LG capable of modifying a computed result obtained by the computing circuit in accordance with data held by the memory circuit 4. The computed result modified by a modification circuit in accordance with the data held by the memory circuit is memorized in the memory cell 9(N) included in each spin cell 1.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: A spin unit provided with a memory cell that stores a value of one spin of an Ising model, a memory cell that stores an interaction coefficient from an adjacent spin which interacts with the corresponding spin, a memory cell that stores an external magnetic field coefficient of the one spin and circuits that determine the next state of the one spin on the basis of a product of a value of each adjacent spin and the corresponding interaction coefficient and the external magnetic field coefficient is configured, the semiconductor device is provided with a spin array where the plural spin units are arranged and connected on a two-dimensional plane on a semiconductor substrate, a random number generator and a bit regulator, the bit regulator operates output of the random number generator and supplies a random bit to all spin units in the spin array via one wire.

Abstract: A semiconductor device includes a spin array in which a plurality of memory cells are disposed in a matrix configuration, a group of a predetermined number of memory cells is collected in units of spin units, and a plurality of the spin units are disposed with an adjacency; a word line provided in correspondence with rows of the memory cells; a bit line pair provided in correspondence with columns of the memory cells; a multiword decoder configured to multiplex a word address according to an input of a multiplicity specify signal to a word line and simultaneously activate a plurality of word lines; and a bit line driver configured to subject a plurality of memory cells, of the memory cells connected to bit line pairs and arrayed in a column direction, activated by the plurality of the word lines to a write operation or a read operation.

Abstract: It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

Abstract: A semiconductor device includes a plurality of spin units individually including a memory cell configured to store values of spins in an Ising model, a memory cell configured to store an interaction coefficient from an adjacent spin that exerts an interaction on the spin, a memory cell configured to store an external magnetic field coefficient of the spin, and an interaction circuit configured to determine a subsequent state of the spin. The spin units individually include a random number generator configured to supply the random number to the plurality of the spin units and generate two-valued simulated coefficients of two values or simulated coefficients of three values in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient.

Abstract: A semiconductor device in which a ground state of an Ising model is realized, includes a spin array in which a spin unit is formed, the spin unit including a memory cell storing a value of one spin in an Ising model, a memory cell storing an interaction coefficient from an adjacent spin interacting with the spin, a memory cell storing an external magnetic field coefficient of the spin, and a circuit deciding a next state of the spin by binary majority decision logic based on a product of the value of each of the adjacent spins and the corresponding interaction coefficient, and the external magnetic field coefficient. The spin array is formed by having a plurality of the spin units, each having each spin allocated thereto, arranged and connected on a two-dimensional plane on a semiconductor substrate in the state where a topology of the Ising model is maintained.

Abstract: In a semiconductor device which calculates an interaction model, a technique capable of executing interaction calculation in non-synchronization with a clock is provided. The semiconductor device includes a plurality of units each of which includes: a first memory cell for storing a value indicating a state of one node of an interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node; and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient.

Abstract: A semiconductor device capable of easily and properly detecting a defective element unit(s) and a quality management method for the semiconductor device are suggested. A semiconducting device simulating interactions between nodes in an interaction model is equipped with a quality management unit for managing the quality of each element unit provided corresponding to each node, wherein the quality management unit executes a specified quality test of each element unit, compares test results of the quality test with pre-given results to be obtained from the quality test, and detects a defective memory cell(s) and a defective element unit(s) based on the comparison results.

Abstract: A semiconductor device has a plurality of units, each of which includes a first memory cell that stores a value indicating a state of one node of an interaction model, a second memory cell that stores an interaction coefficient indicating an interaction from a node connected to the one node, and a third memory cell that stores a bias coefficient of the one node. Furthermore, the semiconductor device has a computing circuit that determines a value indicating a next state of the one node based on a value indicating a state of the connected node, the interaction coefficient and the bias coefficient. Also, each of the second memory cell and the third memory cell in the plurality of units includes multi-valued memory cells.

Abstract: In an optical transmission system including at least one ring network configured by plural nodes, each node of the ring network is provided with the optical switch having connection configuration that the output in at least two directions of a signal input to the node is allowed and the output of the optical switch functions as input to another node included in the plural nodes.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.