Abstract: A memory cell includes a power supply line extending in a Y-direction and configured to supply a power supply voltage. A well tap cell includes: a power supply line extending in the Y-direction, electrically connected to the power supply line, and configured to supply the power supply voltage; and a line formed in an M1 line layer, extending in an X-direction, electrically connected to the power supply line, and configured to supply the power supply voltage. The well tap cell supplies the power supply voltage to an N-well or a P-type substrate of the memory cell.

Abstract: Transistors (N1 to N12) corresponding to drive transistors (PD1, PD2), access transistors (PG1, PG2), read drive transistor (RPD1), and read access transistor (RPG1) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. The transistors (P1, P2) overlap the transistors (N3, N8), respectively, in plan view.

Abstract: Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.

Abstract: Nanosheets 21a to 21d are formed in line in this order in the X direction, and nanosheets 21e to 21h are formed in line in this order in the X direction. Faces of the nanosheets 21c, 21f, and 21g on the first side as one of the opposite sides in the X direction are exposed from gate interconnects 31c, 31e, and 31f, respectively. Faces of the nanosheets 21a, 21b, 21d, 21e, and 21h on the second side as the other side in the X direction are exposed from gate interconnects 31a to 31d and 31g, respectively.

Abstract: Transistors (N3, N4) corresponding to a drive transistor (PD1), transistors (N5, N6) corresponding to a drive transistor (PD2), transistors (N7, N8) corresponding to an access transistor (PG1), and transistors (N1, N2) corresponding to an access transistor (PG2) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. Further, the transistors (P1, P2) overlap the transistors (N3, N6) in plan view.

Abstract: Transistors (N1 to N12) corresponding to drive transistors (PD1, PD2), access transistors (PG1, PG2), read drive transistor (RPD1), and read access transistor (RPG1) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. The transistors (P1, P2) overlap the transistors (N3, N8), respectively, in plan view.

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects provided in I/O cell rows are connected to a power supply interconnect provided between the I/O cell rows via power supply interconnects. The power supply interconnect is thicker than the in-row power supply interconnects.

Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects provided in I/O cell rows are connected to a power supply interconnect provided between the I/O cell rows via power supply interconnects. The power supply interconnect is thicker than the in-row power supply interconnects.

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects (21a to 21d) provided in I/O cell rows (10A, 10B) are connected to a power supply interconnect (23) provided between the I/O cell rows (10A, 10B) via power supply interconnects (25a to 25d). The power supply interconnect (23) is thicker than the in-row power supply interconnects (21a to 21d).

Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

Abstract: In a semiconductor integrated circuit employing power gating, a control input signal is propagated to one or more first power switches through a first propagation path and to one or more second power switches through a second propagation path. A restoration determination circuit receives a first signal of the first propagation path and a second signal of the second propagation path and generates a control output signal. When the control signal performs restoration transition, the restoration determination circuit causes the control output signal to perform the restoration transition in accordance with a later timing of timings of restoration transitions of the first and second signals.

Abstract: In a semiconductor integrated circuit employing power gating, a control input signal is propagated to one or more first power switches through a first propagation path and to one or more second power switches through a second propagation path. A restoration determination circuit receives a first signal of the first propagation path and a second signal of the second propagation path and generates a control output signal. When the control signal performs restoration transition, the restoration determination circuit causes the control output signal to perform the restoration transition in accordance with a later timing of timings of restoration transitions of the first and second signals.

Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects (21a to 21d) provided in I/O cell rows (10A, 10B) are connected to a power supply interconnect (23) provided between the I/O cell rows (10A, 10B) via power supply interconnects (25a to 25d). The power supply interconnect (23) is thicker than the in-row power supply interconnects (21a to 21d).

Abstract: The present disclosure allows for reducing parasitic capacitance of a bit line, and a drop in access performance in an SRAM cell including fin-type transistors. The SRAM cell is defined by transistors each of which has a fin structure and by a local metal interconnection layer. Bit lines are formed on the local metal interconnection layer, and diffusion layer contacts corresponding to bit line nodes are connected through vias to the bit lines.

Abstract: The present disclosure allows for reducing parasitic capacitance of a bit line, and a drop in access performance in an SRAM cell including fin-type transistors. The SRAM cell is defined by transistors each of which has a fin structure and by a local metal interconnection layer. Bit lines are formed on the local metal interconnection layer, and diffusion layer contacts corresponding to bit line nodes are connected through vias to the bit lines.

Abstract: A power generation block configured to generate internal power by a charge pump circuit and a power supply control block configured to control the power generation block are provided. First and second power supply interconnects individually separated from an external power supply interconnect are connected to the power generation block and the power supply control block, respectively. At least any one of the power supply interconnects is provided with a filter section configured to remove noise propagating through the power supply interconnect.

Abstract: In a semiconductor storage device, either two memory cell gates TG or a memory cell gate TG and a bit-line connecting gate SW are formed in every set of n-type doped regions OD at the intersections with word lines WL or bit-line selecting lines KS. A portion near the center of the set of n-type doped regions OD serves as a source/drain region shared by two gates, whereas portions near both ends thereof serve as source/drain regions for respective gates. Each of the source/drain regions is connected to a storage electrode SN of a memory cell capacitor via a storage contact CA or is connected to a sub bit line or a main bit line via a sub-bit-line contact CH and/or a via of a metal interconnection. A pattern formed of four memory cell gates TG and four bit-line connecting gates SW is repeated.