Patents by Inventor Masanobu Hirose
Masanobu Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8488358Abstract: In a semiconductor storage device, either two memory cell gates TG or a memory cell gate TG and a bit-line connecting gate SW are formed in every set of n-type doped regions OD at the intersections with word lines WL or bit-line selecting lines KS. A portion near the center of the set of n-type doped regions OD serves as a source/drain region shared by two gates, whereas portions near both ends thereof serve as source/drain regions for respective gates. Each of the source/drain regions is connected to a storage electrode SN of a memory cell capacitor via a storage contact CA or is connected to a sub bit line or a main bit line via a sub-bit-line contact CH and/or a via of a metal interconnection. A pattern formed of four memory cell gates TG and four bit-line connecting gates SW is repeated.Type: GrantFiled: March 30, 2007Date of Patent: July 16, 2013Assignee: Panasonic CorporationInventor: Masanobu Hirose
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Patent number: 8151173Abstract: Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform.Type: GrantFiled: August 18, 2008Date of Patent: April 3, 2012Assignee: Panasonic CorporationInventors: Masanobu Hirose, Masahisa Iida
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Patent number: 7821805Abstract: To secure a sufficient read-out voltage even when lines are arranged at a fine pitch, a semiconductor memory device including: a memory array in which a plurality of memory cells are arranged in rows and columns; and a plurality of bit lines associated with the respective columns of the memory cells is provided. The bit lines include main bit lines and sub bit lines to have a hierarchical structure, the main bit lines are divided among a plurality of interconnection layers, and a distance between the main bit lines in one of the interconnection layers is larger than a distance between the sub bit lines.Type: GrantFiled: July 25, 2008Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventor: Masanobu Hirose
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Patent number: 7643366Abstract: A plurality of memory macros, to which first power is supplied, and a logic circuit block, to which second power is supplied, are provided. The memory macros are collectively disposed as a memory block on a semiconductor chip, and memory power wires for supplying the first power to the memory macros that form the memory block are provided over the memory block.Type: GrantFiled: May 3, 2007Date of Patent: January 5, 2010Assignee: Panasonic CorporationInventors: Toshihiro Nakamura, Masanobu Hirose
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Publication number: 20090135639Abstract: In a semiconductor storage device, either two memory cell gates TG or a memory cell gate TG and a bit-line connecting gate SW are formed in every set of n-type doped regionsOOD at the intersections with word lines WL or bit-line selecting lines KS. A portion near the center of the set of n-type doped regions OD serves as a source/drain region shared by two gates, whereas portions near both ends thereof serve as source/drain regions for respective gates. Each of the source/drain regions is connected to a storage electrode SN of a memory cell capacitor via a storage contact CA or is connected to a sub bit line or a main bit line via a sub-bit-line contact CH and/or a via of a metal interconnection. A pattern formed of four memory cell gates TG and four bit-line connecting gates SW is repeated.Type: ApplicationFiled: March 30, 2007Publication date: May 28, 2009Inventor: Masanobu Hirose
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Publication number: 20090089646Abstract: Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform.Type: ApplicationFiled: August 18, 2008Publication date: April 2, 2009Inventors: Masanobu Hirose, Masahisa Iida
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Publication number: 20090034314Abstract: To secure a sufficient read-out voltage even when lines are arranged at a fine pitch, a semiconductor memory device including: a memory array in which a plurality of memory cells are arranged in rows and columns; and a plurality of bit lines associated with the respective columns of the memory cells is provided. The bit lines include main bit lines and sub bit lines to have a hierarchical structure, the main bit lines are divided among a plurality of interconnection layers, and a distance between the main bit lines in one of the interconnection layers is larger than a distance between the sub bit lines.Type: ApplicationFiled: July 25, 2008Publication date: February 5, 2009Inventor: Masanobu HIROSE
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Patent number: 7330386Abstract: In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. During a stand-by period, each of the source lines is controlled to be in a state where the source bias potential is supplied and, during an active period, one or more of the source lines which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.Type: GrantFiled: July 25, 2006Date of Patent: February 12, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Naoki Kuroda, Masanobu Hirose
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Publication number: 20070274149Abstract: A plurality of memory macros, to which first power is supplied, and a logic circuit block, to which second power is supplied, are provided. The memory macros are collectively disposed as a memory block on a semiconductor chip, and memory power wires for supplying the first power to the memory macros that form the memory block are provided over the memory block.Type: ApplicationFiled: May 3, 2007Publication date: November 29, 2007Inventors: Toshihiro Nakamura, Masanobu Hirose
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Publication number: 20070030744Abstract: Source potential connection transistors, each supplying a source control potential from a source potential wiring to a source node, are disposed so as to be dispersed in a memory cell array. In addition, a source potential control circuit is disposed inside a row decoder block. With this configuration, the number of the cells connected to each word line can be increased, and the area of the memory core can be reduced. Furthermore, the pattern shape of the diffusion layer constituting the source potential connection transistor is made the same as that of the diffusion layer of a memory cell transistor, whereby mask creation can be facilitated.Type: ApplicationFiled: July 18, 2006Publication date: February 8, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshihiro Nakamura, Naoki Kuroda, Masanobu Hirose
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Publication number: 20070019490Abstract: In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. During a stand-by period, each of the source lines is controlled to be in a state where the source bias potential is supplied and, during an active period, one or more of the source lines which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.Type: ApplicationFiled: July 25, 2006Publication date: January 25, 2007Inventors: Naoki Kuroda, Masanobu Hirose
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Patent number: 7035128Abstract: In a DRAM memory cell including an access Tr and a cell capacitor, a depletion type MOSFET is used for each of the access Tr and the cell capacitor. Thus, an operation margin can be increased and the number of necessary power supplied can be reduced, compared to a known DRAM.Type: GrantFiled: December 15, 2003Date of Patent: April 25, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yuji Yamasaki, Masanobu Hirose
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Patent number: 7002866Abstract: In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.Type: GrantFiled: March 14, 2005Date of Patent: February 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanobu Hirose, Masahisa Iida, Kiyoto Ohta
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Publication number: 20050157527Abstract: In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.Type: ApplicationFiled: March 14, 2005Publication date: July 21, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masanobu Hirose, Masahisa Iida, Kiyoto Ohta
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Patent number: 6898109Abstract: In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.Type: GrantFiled: November 20, 2002Date of Patent: May 24, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanobu Hirose, Masahisa Iida, Kiyoto Ohta
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Patent number: 6842388Abstract: The present invention is a semiconductor memory device provided with bit line pairs to which a plurality of memory cells are attached, a plurality of precharge circuits for precharging the bit line pairs to a first voltage that is different from a mean value between a high level and a low level, a bit line precharge power line for supplying the first voltage for precharging to the precharge circuits, a capacitor, a charging circuit for charging the capacitor, and transfer gate circuits for controlling connection and disconnection of the capacitor and the bit line precharge power line. The transfer gate circuits are controlled so that the capacitor and the precharge power line are connected during precharging of the bit line pairs. Thus, precharging of the bit lines can be performed at high speeds with high precision.Type: GrantFiled: November 19, 2002Date of Patent: January 11, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenichi Origasa, Kiyoto Ohta, Masanobu Hirose
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Publication number: 20040136219Abstract: In a DRAM memory cell including an access Tr and a cell capacitor, a depletion type MOSFET is used for each of the access Tr and the cell capacitor. Thus, an operation margin can be increased and the number of necessary power supplied can be reduced, compared to a known DRAM.Type: ApplicationFiled: December 15, 2003Publication date: July 15, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yuji Yamasaki, Masanobu Hirose
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Patent number: 6628162Abstract: A semiconductor integrated circuit includes a functional circuit and a power source voltage generating circuit used for operating the functional circuit. In the power source voltage generating circuit, output stage transistors are driven by comparing a plurality of reference voltages produced by a plurality of resistors connected in series to one another with output voltages of a plurality of differential amplifiers connected in parallel to one another and varying gate voltages.Type: GrantFiled: November 16, 2001Date of Patent: September 30, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kondo, Kiyoto Ohta, Yuji Yamasaki, Toshikazu Suzuki, Masanobu Hirose
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Publication number: 20030095429Abstract: In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.Type: ApplicationFiled: November 20, 2002Publication date: May 22, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masanobu Hirose, Masahisa Iida, Kiyoto Ohta
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Publication number: 20030095430Abstract: The present invention is a semiconductor memory device provided with bit line pairs to which a plurality of memory cells are attached, a plurality of precharge circuits for precharging the bit line pairs to a first voltage that is different from a mean value between a high level and a low level, a bit line precharge power line for supplying the first voltage for precharging to the precharge circuits, a capacitor, a charging circuit for charging the capacitor, and transfer gate circuits for controlling connection and disconnection of the capacitor and the bit line precharge power line. The transfer gate circuits are controlled so that the capacitor and the precharge power line are connected during precharging of the bit line pairs. Thus, precharging of the bit lines can be performed at high speeds with high precision.Type: ApplicationFiled: November 19, 2002Publication date: May 22, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kenichi Origasa, Kiyoto Ohta, Masanobu Hirose