Abstract: A silicon carbide semiconductor device has a semiconductor substrate, a trench gate structure disposed in the semiconductor substrate, a first electrode electrically connected to an impurity region and a bae layer of the semiconductor substrate, a second electrode connected to a substrate, and an interlayer insulating film disposed between a gate electrode and the first electrode. The trench gate structure includes a gate insulating film disposed in a trench of the semiconductor substrate and the gate electrode disposed on the gate insulating film. A portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one of nitrogen, hydrogen or phosphorous. The interlayer insulating film has a contact insulating film that is in contact with the gate electrode. The contact insulating film is provided by a deposited film.

Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a low-concentration semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a semiconductor layer of the second conductivity type in the active region and a semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the semiconductor layer, and the second semiconductor layer is not in contact with a surface of the semiconductor substrate.

Abstract: A semiconductor device includes, as a semiconductor region in which semiconductor layers are formed, an active region through which current flows and an edge termination structure region outside the active region and in which an edge termination structure is formed. The semiconductor device includes as the semiconductor layers: a drift layer of a first conductivity type and a base layer of a second conductivity type, in contact with the edge termination region; and includes an interlayer insulating film provided on the semiconductor region, on a side thereof where the base layer is formed. The edge termination region has a first semiconductor layer of the second conductivity type, continuous from the base layer and having an outer peripheral end not in contact with the interlayer insulating film, and a second semiconductor layer of the first conductivity type, in contact with the first semiconductor layer and forming a first PN junction therewith.

Abstract: A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.

Abstract: At an upper surface of a gate electrode, a recess occurs due to etching back of poly-silicon for forming the gate electrode. At an upper surface of an interlayer insulating film, a recess occurs in a portion that opposes in a depth direction, the recess of the upper surface of the gate electrode. A barrier metal includes sequentially stacked first to fourth metal films. The first metal film is a titanium nitride film that covers the surface of the interlayer insulating film and has an opening that exposes the recess of the upper surface of the interlayer insulating film. The second metal film is a titanium film that covers the first metal film and the source electrode, and is in contact with the interlayer insulating film, in the opening of the first metal film. The third and fourth metal films are a titanium nitride film and a titanium film, respectively.

Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a low-concentration semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a semiconductor layer of the second conductivity type in the active region and a semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the semiconductor layer, and the second semiconductor layer is not in contact with a surface of the semiconductor substrate.

Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a first semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a third semiconductor layer of the second conductivity type in the active region and a third semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the third semiconductor layer, and the second semiconductor layer is not in contact with a surface of the first semiconductor layer.

Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.

Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.

Abstract: At an upper surface of a gate electrode, a recess occurs due to etching back of poly-silicon for forming the gate electrode. At an upper surface of an interlayer insulating film, a recess occurs in a portion that opposes in a depth direction, the recess of the upper surface of the gate electrode. A barrier metal includes sequentially stacked first to fourth metal films. The first metal film is a titanium nitride film that covers the surface of the interlayer insulating film and has an opening that exposes the recess of the upper surface of the interlayer insulating film. The second metal film is a titanium film that covers the first metal film and the source electrode, and is in contact with the interlayer insulating film, in the opening of the first metal film. The third and fourth metal films are a titanium nitride film and a titanium film, respectively.

Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.

Abstract: In a termination structure region, a first semiconductor layer of a first conductivity type, with an impurity concentration lower than that of a semiconductor substrate, is provided on the substrate of the first conductivity type. A second semiconductor layer of a second conductivity type is provided on a first side of the first semiconductor layer, opposite to a second side facing the substrate. Trenches penetrate the second semiconductor layer. At the first side in the first semiconductor layer, a first semiconductor region of the second conductivity type, with an impurity concentration higher than that of the second semiconductor layer, is provided at a side closer to an active region, contacting the second semiconductor layer. A second semiconductor region of the first conductivity type is provided in the second semiconductor layer, outside and adjacent to one of the trenches that is disposed at a farthest position from the active region.

Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: In a termination structure region, a first semiconductor layer of a first conductivity type, with an impurity concentration lower than that of a semiconductor substrate, is provided on the substrate of the first conductivity type. A second semiconductor layer of a second conductivity type is provided on a first side of the first semiconductor layer, opposite to a second side facing the substrate. Trenches penetrate the second semiconductor layer. At the first side in the first semiconductor layer, a first semiconductor region of the second conductivity type, with an impurity concentration higher than that of the second semiconductor layer, is provided at a side closer to an active region, contacting the second semiconductor layer. A second semiconductor region of the first conductivity type is provided in the second semiconductor layer, outside and adjacent to one of the trenches that is disposed at a farthest position from the active region.

Abstract: An interlayer insulating film is formed on a gate insulating film and a gate electrode, and the interlayer insulating film is opened forming contact holes. Next, the interlayer insulating film and regions exposed by the contact holes are covered by a titanium nitride film, and the titanium nitride film is etched to remain only at portions of the gate insulating film and the interlayer insulating film exposed in the contact holes. The interlayer insulating film and the regions exposed by the contact holes are covered by a nickel film, and after the nickel film directly contacting the interlayer insulating film is removed, the nickel film is heat treated and a nickel silicide layer is formed.

Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.