Abstract: The present invention discloses a handpiece having a root canal length measurement function, wherein a signal circuit, which is specifically provided for sending measurement signals from a root canal length measurement circuit to a measurement probe mounted on a head provided at the tip of the handpiece, is incorporated in the handpiece, and the signal circuit is electrically connected to the measurement probe via a contact piece in the vicinity of the measurement probe. Therefore, it is not necessary to connect the signal circuit for measurement by way of the outside of the handpiece. In addition, this structure improves the operability of the handpiece because there is no lead wire for connection. Furthermore, this structure eliminates the troublesome task of externally connecting lead wires to the head of the handpiece, which would otherwise be required at each treatment time.

Abstract: A semiconductor device has a function of reading device information specific to the device as and when required. The semiconductor device has storage units for storing plural pieces of device information and a selector for selecting a predetermined one of the information pieces stored in the storage units when a device information read mode is set, so that the read information may match device data such as a manufacturer name and part name printed on the semiconductor device.

Abstract: A nonvolatile semiconductor memory apparatus of a reference type is provided with a memory circuit, reference circuit and differential amplifier. A drain current of a reference cell transistor is formed such that it becomes almost half a drain current of a memory cell transistor, thereby enabling the memory circuit to be in symmetric relation with the reference circuit. Therefore, a parastic capacitance in the memory circuit is made to be almost the same as that of the reference circuit, and thus a difference in noise level between a noise input to one input of the differential amplifier and a noise input to the other input of the differential amplifier is made to be almost zero, thereby speeding up the data read-out operation of the semiconductor memory apparatus.

Abstract: A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors.

Abstract: A semiconductor memory having address buffer means, memory cell means, word line selection means, bit line selection means, an output buffer, first address generation means connected to the address buffer means, for providing and address for specifying a group of data pieces, and second address generation means for providing addresses for specifying the data pieces, respectively, the semiconductor memory comprising first reading means for selecting and reading a group of data pieces through one of the word line selection means and bit line selection means according to an address provided by the first address generation means, second reading means for selecting the data pieces, which have been selected and read according to the address provided by the first address generation means, through one of the bit line selection means and word line selection means according addresses provided by the second address generation means and providing them to the output buffer; and pre-reading means for reading another group

Abstract: When a current flows through a selected memory cell transistor at the time of data reading, the gate voltage of an n-channel MOS transistor, which makes up the current flowing through the load, rises. Thus, when a current flows through a selected memory cell transistor at the time of data reading, the current through the load is increased so that the time required for data reading when the current flows through the selected memory cell transistor can be shortened and the data reading can be effected at a high speed.

Abstract: A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors.

Abstract: A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors.

Abstract: An electrically programmable and electrically erasable non-volatile semiconductor memory device having an array of single transistor cells is provided. The disclosed device protects against reading faults even in the event that adjacent transistors may be over erased. Each of the cell transistor rows has an associated word line and an associated select element. The select elements are connected to the sources of their associated cell transistors and are arranged to activate those cell transistors only when their associated word line is selected. Cell transistors in unselected rows are not activated and thus do not interfere with reading even if they are in an over erased condition.

Abstract: An erasable non-volatile semiconductor memory device has a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detects the write status of each memory cell by a differential type detection circuit through first and second bit lines connected to the two cell transistors. Further, the erasable non-volatile semiconductor memory device sets all cell transistors constructing a plurality of the memory cells to the erasing status or write status in entirety, and controls the connection of the first and second bit lines for executing the read/write test. Therefore, the erasable non-volatile semiconductor memory device according to the present invention can reduce the erasing process cycles, which requires a long time, falsely read out the "0" data and "1" data without writing actual data into each memory cell to shorten the test time, and thus can supply a low price product.

Abstract: A semiconductor device for absorbing a noise comprises a first and second buffer. The first and second buffers receive an external signal having a rising edge and a falling edge, and performs waveform shaping thereof to produce an output signal. The first buffer, which issues an output signal for controlling the internal circuits of a chip of the semiconductor device so as to make the chip's internal circuits active/stand-by, is not sensitive to the rising edge of the external signal, but is sensitive to the falling edge of the same external signal. The second buffer, which issues an output signal for controlling an output circuit of a chip of the semiconductor device so as to make the output circuit active/stand-by, is sensitive to both the rising and the falling edges of the external signal.

Abstract: A NAND gate circuit which can be used for a decoder circuit, includes a high potential voltage source (V.sub.cc), an output terminal (V.sub.OUT), and a load element (T.sub.1) connected between the high potential electric voltage source (V.sub.cc) and the output terminal (V.sub.OUT). A driving circuit is serially connected with the output terminal (V.sub.OUT), and a low potential voltage source (V.sub.ss), and has a plurality of driving transistors (T.sub.2, T.sub.3) which are serially arranged. An input signal is applied to each gate. At least one transistor, constituting the driving circuit, has a driving performance different from the other transistors of the driving circuit. An ideal NAND gate circuit can be provided in which erroneous operation due to noise can be effectively prevented by setting the input threshold voltage to a constant voltage no matter what the combination of the input signals.

Abstract: A power supply potential rising detection circuit comprises a transistor having a control gate and a floating gate, connected in series with a load element between first and power supply terminals. A first potential is applied to the control gate, the first potential being dependent on the power supply potential at the first power supply terminal. A switching element is operatively connected to the floating gate and controlled by a second potential dependent on the power supply potential, and reduces the potential of the floating gate and turns off the transistor when the power supply potential reaches a predetermined value, thereby outputting a power supply potential rising detection signal from the series connection point between the load element and the transistor.

Abstract: A semiconductor memory device has a decoder circuit. The decoder circuit includes a load transistor T.sub.1, a NAND gate circuit, i.e., a driver circuit serially connected to the load transistor T.sub.1 and includes a plurality of driving transistors T.sub.2 to T.sub.5 serially connected each other. An inverter IV is connected to the node N.sub.1 formed between the load transistor T.sub.1 and the NAND gate circuit. An additional load current increasing device T.sub.8 is connected to the node N.sub.1 or to a contact portion formed between two transistors arranged adjacently to each other in the NAND gate circuit. The load current increasing device T.sub.8 is operable only in the reading mode for increasing the load current and thus to increase the threshold voltage level of the decoder circuit up to about V.sub.cc /2, thereby preventing erroneous operation of the decoder and the memory cell array.

Abstract: In a video camera system composed of exchangeable lens devices interchangeably mountable on a camera body having an image pick up element to generate a signal corresponding to a light image projected thereon by an imaging lens of the exchangeable lens device in use, a signal processing circuit responsive to the signal from the image pick up element for providing a color video signal, and a white balance adjusting circuit for correcting the white balance of the color video signal; there are provided a memory for storing white balance correction data characteristic of each of the exchangeable lens devices; and a circuit responsive to the white balance correction data which is characteristic of the one of the exchangeable lens devices mounted on the camera body for correcting operation of the white balance adjusting circuit.

Abstract: An automatic focus control apparatus that makes effective use of the chromatic aberration of a lens to detect focus position information on the basis of amplitude values of color signals, whereby the apparatus can be simplified in arrangement and which can prevent the image quality from being deteriorated.

Abstract: A data read circuit for use in a semiconductor memory device including an input node operatively connected to a bit line; an output node for outputting a read-out signal; a first transistor connected between the input node and the output node and turned ON and OFF in accordance with a potential of the bit line connected to a selected memory cell transistor; a second transistor connected to the output node and turned ON for a predetermined period after an address signal is changed; and a third transistor connected to the second transistor in parallel and turned ON and OFF in accordance with the read-out signal so that the third transistor is turned OFF when the selected memory cell transistor is turned ON.

Abstract: A semiconductor memory device, including a plurality of programmable read only memory cells arranged at intersection points of a matrix formed by a plurality of word-lines and bit-lines crossing each other, independently having first column transfer gate transistors located between a programming circuit and the bit-lines to transfer a programming data signal from the programming circuit to a selected memory cell located on one of the bit-lines when the memory device is in a programming mode and second column transfer gate transistors located between a sense amplifier and the bit-lines to transfer a read out data signal from a selected memory cell located on one of the bit-lines to a sensing amplifier when the memory device is in a reading mode.

Abstract: A semiconductor integrated circuit device includes a memory cell array, a decoder circuit, a selection circuit and a plurality of input/output terminals. The selection circuit is connected to one of the terminals and includes a high voltage detector circuit for producing a control signal only when a predetermined voltage higher than a power source voltage is applied to one of the terminals. The selection circuit further includes a latch circuit connected to the terminals other than the one terminal, for latching an input signal in response to a control signal produced from the high voltage detector circuit. When a predetermined high voltage is applied to the high voltage detector circuit through one of the terminals, the signal input from the other terminals is latched, in response to the control signal. The status of the memory cell array and the decoder circuit is made to a predetermined specific mode, based upon the latched signal.

Abstract: A programming circuit for a programmable read only memory device receiving a data signal to be programmed including a power supply terminal for receiving a first voltage in a read mode and a second voltage as a programming voltage which is a higher voltage than the first voltage in a program mode; an inverter circuit for converting an amplitude of the data signal in the program mode, the inverter including a load element and a first transistor having a drain connected to the load element and a gate receiving the data signal; and a switching circuit connected between the power source terminal and the load element for supplying the second voltage in the program mode and inhibiting a supply of the first voltage in the read mode.