Abstract: A decoder circuit fabricated in an IC memory chip and provided to respective word-lines and respective bit-lines of an IC memory matrix fabricated in the IC memory chip, is provided for selecting an EPROM cell which is placed on an intersection point of the word-line and the bit-line, to program a datum into the EPROM cell by using a high power supply voltage when the decoder circuit operates under a programming mode and to read out a datum stored in the EPROM cell by using a low power supply voltage when the decoder circuit operates under a reading mode, receiving an address signal from the exterior of the decoder circuit. The decoder circuit comprises a NAND gate having its load and a CMOS invertor.

Abstract: A semiconductor memory device including a substrate having one conductivity type; read only memory element formed in the substrate for storing fixed information, the element having a control gate, a floating gate, a source region, and a drain region, both of the regions having an opposite conductivity type to that of the substrate; a first region having the above one conductivity type which surrounds the element; a light shield layer, connected to the source region and the first region, for covering the element; a second region having the opposite conductivity type which is located outside of the first region for taking out the drain region; and a well region having the opposite conductivity type, the well region linking the drain region and the second region, a part of the first region being formed in the well.

Abstract: A decoder circuit of a semiconductor memory device includes a plurality of logic gates each consisted by a load transistor and drive transistors generating a line selection signal corresponding to input address signals, and a power source control circuit for controlling the power source voltage supplied to the logic gate corresponding to a mode designation signal which is a normal mode signal or an all selection mode signal. According to the present invention, when the all selection mode signal is input to the power source control circuit, the all selection mode state of the decoder circuit is obtained by pulling down the power source voltage supplied to the logic gate.

Abstract: A ROM circuit is used in place of a conventional fuse type ROM which is incorporated in a semiconductor integrated circuit network together with other circuit blocks on a chip. The ROM circuit comprises a first transistor having a control and a floating gate and a depletion type second transistor having a gate formed as an extension of the floating gate. The second transistor outputs a high level control signal if hot electrons have been accumulated on the floating gate of the first transistor by the application of a predetermined high level input signal to the control gate thereof, and outputs a low level signal when the high level input signal has not been provided to the control gate. The first transistor is freed from a soft write problem because it is separated from a voltage source in the read mode.

Abstract: A memory system having an erasable programmable read only memory (EPROM) for storing principal data, a read only memory (ROM) for storing key data, and a processing unit for writing or reading the principal data into or from the EPROM under control of the key data. The EPROM has an address converter having a volatile memory for temporarily storing the key data. External address data for wiring the principal data into the EPROM are converted to internal address data by the address converter using the key data stored in the volatile memory; the principal data stored in the EPROM are read out by converting external address data into internal address data, again using the key data stored in the volatile memory. The key data stored in the ROM are read out and applied to the volatile memory during the power turn-on of the memory system, the key data controlling the processing by the processing unit.

Abstract: A programmable read-only memory device comprising a memory cell transistor which has a floating gate and a control gate formed above the floating gate. The programmable read-only memory device further comprises a means for delaying the application timing of a high voltage to the control gate from that of a high voltage to the drain of the memory cell transistor when a data programming operation is performed by applying the high voltage to the control gate and the drain of the memory cell transistor, thereby ensuring reliable a data write operation even at a low programming voltage.

Abstract: A semiconductor memory device includes a plurality of word lines and a plurality of bit lines arranged perpendicular to each other. Memory cells are located at the cross position between each word line and each bit line, and one of the bit lines is selected by the operation of a bit line selection transistor driven by the signal of a column decoder. The bit line selection transistors are separated into a plurality of blocks corresponding to each bit line group, and the bit line selection transistors in each block are arranged along the direction of the bit line. Further, the gates of the bit line selection transistors are arranged perpendicular to the direction of the bit lines, and the gates of the bit line selection transistors are commonly connected to the gates of the corresponding bit line selection transistors in the adjoining bit line selection transistor blocks.

Abstract: An integrated semiconductor circuit device for generating a switching control signal includes a fuse having one terminal connected to a power source, and the other terminal connected to a flip-flop circuit comprising a cross-connected pair of complementary MOS field effect transistor type inverters. The output of the flip-flop circuit can be used as the switching control signal for a semiconductor memory device having a redundant circuit.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks corresponding to output terminals, and a redundancy memory cell block for replacing a faulty memory cell block among the memory cell blocks, the redundancy memory cell block having a first specific area for storing a first predetermined data of electronic signatures. Each of the memory cell blocks having a second specific area for storing a second predetermined data equal to a divided one of the first predetermined data in a one to one correspondence. The semiconductor memory device further includes a circuit for selectively reading, when one of the memory cell blocks is replaced by the redundancy memory cell block, a divided one of the first predetermined data corresponding to the second predetermined data stored inthe memory cell block to be replaced by the redundancy memory cell block. The second predetermined data can be correctly read out even when a faulty memory cell block is replaced with the redundancy memory cell block.

Abstract: An electrically programmable non-volatile semiconductor memory device includes a plurality of word lines; a plurality of bit lines; and cell transistors, each having a control gate connected to the word line, a drain connected to the bit line, and a floating region for storing electrical charges therein are arranged at cross points of the word lines and the bit lines. An information "0" is written in the cell at the cross point by applying a high electric potential to both the selected word line and the selected bit line, and an information "1" is written in the cell by applying a high electric voltage to the word line and a low voltage to the bit line. For the purpose of testing whether or not the cell transistor is good, one control circuit or a plurality of additional control circuits can be used to simultaneously place all word lines and/or all bit lines in a selected state or in non-selected state.

Abstract: An output circuit of a semiconductor device for suppressing erroneous operation due to potential variations of the power supply line or the ground line. The output circuit comprises an output stage inverter connected between the power supply line and the ground line and a clamping circuit for clamping the voltages applied to the output stage inverter. A large instantaneous current which flows through the output stage inverter during a transition of state is greatly suppressed so that erroneous operation is prevented.

Abstract: A semiconductor EPROM device which comprises a plurality of floating gate type memory cell transistors and in which the threshold potential of the memory cell transistors is measured by changing the potential of a second power supply terminal to which is originally connected a high potential used for programming the EPROM device.

Abstract: A junction leakage current compensating circuit for a semiconductor memory device of a charge-storage type in which information can be erased by strong ultraviolet light is disclosed. The device comprises at least one dummy bit line connected to dummy cells incorporated with main memory cells and at least one compensating circuit for detecting the potential of the dummy bit line. The compensating circuit supplies compensating currents to bit lines connected to the main memory cells, responsive to the change of the potential of the dummy bit line.