Abstract: An information processing apparatus includes: a first preprocessing arithmetic device configured to execute preprocessing for analog data from a first sensor; and a first post-processing arithmetic device connected to the first preprocessing arithmetic device and configured to execute post-processing for first preprocessed data, wherein the first preprocessing arithmetic device includes a first processor configured to: receive the analog data from the first sensor and convert the analog data into digital data; output feature data on the basis of a result of execution of feature extraction processing for the digital data; and output the feature data, and the first post-processing arithmetic device includes a second processor configured to: input the feature data; store the feature data in a first memory; and store, in the first memory, recognition result data based on a result of execution of recognition processing for the feature data.

Abstract: An arithmetic processing device includes arithmetic processing units, each having a calculator unit; a scheduler that controls a push instruction to write data to a register file in one of the arithmetic processing units and a pull instruction to read data from the register file; a pull request bus to which the scheduler outputs a pull request and which is connected to the arithmetic processing units; a push request bus to which the scheduler outputs a push request and which is connected to the arithmetic processing units; and a pull data bus that inputs, into the scheduler, pull data read from the register file in response to the pull request. Each of the arithmetic processing units includes a pull data turn-back bus that propagates pull data read from its register file to the pull data bus.

Abstract: An information processing apparatus includes: a first preprocessing arithmetic device configured to execute preprocessing for analog data from a first sensor; and a first post-processing arithmetic device connected to the first preprocessing arithmetic device and configured to execute post-processing for first preprocessed data, wherein the first preprocessing arithmetic device includes a first processor configured to: receive the analog data from the first sensor and convert the analog data into digital data; output feature data on the basis of a result of execution of feature extraction processing for the digital data; and output the feature data, and the first post-processing arithmetic device includes a second processor configured to: input the feature data; store the feature data in a first memory; and store, in the first memory, recognition result data based on a result of execution of recognition processing for the feature data.

Abstract: An information processing system includes: a processor in one information processing apparatus among information processing apparatuses coupled via a ring bus corresponding to a closed-loop bus; and a first memory, wherein the processor: generate a verification request for verification of completion of a write request after issuing the write request to a second memory in the information processing apparatuses; transmit the verification request to a subsequent information processing apparatus; transmit, when a request from a preceding information processing apparatus is not a verification request, the request to the subsequent information processing apparatus; transmit, when the request is a verification request to another information processing apparatus, the verification request and a request to the first memory to the subsequent information processing apparatus in order of receiving; and execute, when the request is a verification request to the one information processing apparatus, processing and generate

Abstract: An arithmetic processing device includes: a memory controller that accesses a main storage device; a plurality of arithmetic processing cores that execute instructions; an instruction controller that controls execution of an access instruction to load and store data in the plurality of arithmetic processing cores from and to the main storage device; and a transfer controller that controls data transfer between the memory controller and the plurality of arithmetic processing cores in accordance with an instruction from the instruction controller.

Abstract: An arithmetic processing device includes arithmetic processing units, each having a calculator unit; a scheduler that controls a push instruction to write data to a register file in one of the arithmetic processing units and a pull instruction to read data from the register file; a pull request bus to which the scheduler outputs a pull request and are connected to the arithmetic processing units; a push request bus to which the scheduler outputs a push request and are connected to the arithmetic processing units; and a pull data bus that inputs, into the scheduler, pull data read from the register file in response to the pull request. The arithmetic processing unit includes a pull data turn-back bus that propagates the pull data read from the register file of the home calculator unit to the pull data bus.

Abstract: An information processing system includes: a processor in one information processing apparatus among information processing apparatuses coupled via a ring bus corresponding to a closed-loop bus; and a first memory, wherein the processor: generate a verification request for verification of completion of a write request after issuing the write request to a second memory in the information processing apparatuses; transmit the verification request to a subsequent information processing apparatus; transmit, when a request from a preceding information processing apparatus is not a verification request, the request to the subsequent information processing apparatus; transmit, when the request is a verification request to another information processing apparatus, the verification request and a request to the first memory to the subsequent information processing apparatus in order of receiving; and execute, when the request is a verification request to the one information processing apparatus, processing and generate

Abstract: An operation processing apparatus includes: a plurality of operation elements; a plurality of first data storages disposed so as to correspond to the respective operation elements and each configured to store first data; and a shared data storage shared by the plurality of operation elements and configured to store second data, each of the plurality of operation elements are configured to perform an operation using the first data and the second data.

Abstract: An arithmetic processing device includes: a memory controller that accesses a main storage device; a plurality of arithmetic processing cores that execute instructions; an instruction controller that controls execution of an access instruction to load and store data in the plurality of arithmetic processing cores from and to the main storage device; and a transfer controller that controls data transfer between the memory controller and the plurality of arithmetic processing cores in accordance with an instruction from the instruction controller.

Abstract: A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

Abstract: An address translation table stores therein an association relation between a logical address and a physical address, change information indicating a change in the association relation when the association relation is changed such that a physical address having been associated with each logical address is associated with a different logical address, and the different logical address. A table control unit, when receiving a command to move data between logical addresses from a CPU, changes the association relation in the address translation table such that a movement-destination logical address is associated with a physical address in which the data is stored, sets change information in a movement-source logical address, and stores the movement-destination logical address as a different logical address associated with the movement-source logical address.

Abstract: Channels have NAND flash memories. Data processing units perform data processing on the NAND flash memories by using the channels according to a data processing command from a CPU. A configuration register stores therein a configuration of groups into which the channels are classified based on processing performances of the respective channels, and stores therein assignments of the data processing units that perform data processing by using the channels contained in each of the groups. The group identifying unit selects a group for performing data processing from among the groups stored in the configuration register based on the data processing command from the CPU, and causes the data processing unit assigned to the selected group to perform the data processing.

Abstract: An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process including: first counting, among blocks each including a plurality of storage areas included in the storage device, number of transfer candidate blocks including the storage areas in which written data is invalidated; second counting, among the blocks, number of reserve blocks in which no data is written in the respective storage areas; determining whether transfer processing is to be started, in accordance with a result of comparing a count value of the first counting with a count value of the second counting; and transferring only valid data written in the respective storage areas of the transfer candidate block to the reserve block when it is determined that the transfer processing is to be started.

Abstract: An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process comprising: selecting a logical address identifying data stored in the storage device; acquiring a physical address associated with the selected logical address, from a conversion table storing therein the logical addresses and physical addresses identifying the storage areas in which the data is stored in association with each other; determining whether the stored data indicated by the acquired physical address is to be transferred; transferring the stored data to another storage area when it is determined that the data is to be transferred; and updating the physical address associated with the selected logical address in the conversion table to the physical address indicating the other storage area.

Abstract: A semiconductor circuit apparatus includes a controller configured to output a control signal, an outputting part configured to output the control signal outside of the semiconductor circuit apparatus, a condition holding part configured to hold a generating condition and an output condition of a trigger signal, a trigger signal generator configured to generate the trigger signal, if the control signal satisfies the generating condition, a delay controller configured to give a delay to the trigger signal based on the output condition, and a selector configured to be disposed between the controller and the outputting part and to selectively output the trigger signal delayed at the delay controller to the outputting part instead of the control signal output from the controller based on the output condition.

Abstract: An information processing device includes: a storage device that has a plurality of storage areas; a detection unit that carries out error detection from read data out of the storage area belonging to the storage device; a readout unit that, in a case that the detection unit detects an error, identifies an area where error occurrence is estimated including a storage area in which the data where the error is detected is written and carries out readout of data individually from each storage area in the identified area; and a movement unit that, in a case of detecting an error from the data read out by the readout unit, moves the data to another storage area.

Abstract: An information processing apparatus includes a cyclic frequency counter that updates a count value when a process that determines whether data stored in each of multiple storage areas included in NAND devices is targeted for a move has been executed on all pieces of data stored in the NAND devices. Furthermore, the information processing apparatus includes a table storing unit that stores therein, when data is stored in one of the NAND devices, the count value of the cyclic frequency counter associated with the data. Furthermore, the information processing apparatus includes a cyclic reference control unit that compares, for each data stored in the NAND devices, a value stored in the table storing unit with the count value of the cyclic frequency counter and then determines whether each piece of data is targeted for a move.

Abstract: A nonvolatile memory manages stored data by using physical addresses. By using logical addresses associated with the physical addresses, an arithmetic processing unit outputs a process instruction to be performed on data stored in the nonvolatile memory. On the basis of the process instruction output by the arithmetic processing unit, an access control unit detects an instruction to move the data stored in the nonvolatile memory. An address conversion table control unit stores therein the association relationship between the physical addresses and the logical addresses. When the access control unit detects the instruction to move the data, the address conversion table control unit changes the association relationship such that a logical address at the move destination is associated with the physical address in which the data is stored.

Abstract: An information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, cause the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.

Abstract: A memory controller receives a read request and also issues a patrol request at a predetermined time interval so as to determine whether any error occurs in data stored in a DIMM. Furthermore, the memory controller generates a patrol address that is the subject of the subsequently issued patrol request. When the memory controller receives a read request, the memory controller compares the patrol address with the read address that is the subject of the received read request. When the read address matches the patrol address, the memory controller cancels the issuance of the subsequent patrol request.