Patents by Inventor Masanori Higeta

Masanori Higeta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130339591
    Abstract: When a relaying apparatus receives communication unit data transmitted from a processing apparatus that performs data processing, the relaying apparatus extracts preset data from the received communication unit data as trace information and calculates the number of pieces of the received communication unit data. History information of the received communication unit data is selected from the extracted trace information and statistical information obtained from the result of the calculation. The selected information is recorded in a storage apparatus available to the processing apparatus.
    Type: Application
    Filed: August 8, 2013
    Publication date: December 19, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Jin Takahashi, Masanori Higeta, Shintaro Itozawa, Masahiro NISHIO, Hiroshi Nakayama, Junji Ichimiya
  • Publication number: 20130297895
    Abstract: A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 7, 2013
    Inventors: Hideyuki SAKAMAKI, Hidekazu OSANO, Hiroshi NAKAYAMA, Kazuya TAKAKU, Masanori HIGETA
  • Publication number: 20130275484
    Abstract: A separation circuit separates a 32-bit dividend, (e.g., 1695) into 4-bit segments and outputs 9 separated dividends. The position of each dividend counted from the dividend having the lowest bit is i. A first output circuit concatenates at the end of a dividend, 0s of number equal to an integer multiple of 4 bits. Each calculation circuit outputs an 8-bit quotient, a numerical value created by the first output circuit divided by 3(=2n?1 and n=2), and outputs from a second output circuit, a first bit sequence that is the upper 4 bits of the 8-bit quotient, and a second bit sequence in which i sets of lower 4 bits of the 8-bit quotient are arranged. A quotient addition circuit outputs, as a quotient of 1695 divided by 3, the sum of values each including the first bit sequence at upper bits and the second bit sequence at lower bits.
    Type: Application
    Filed: June 6, 2013
    Publication date: October 17, 2013
    Inventors: Hidekazu Osano, HIDEYUKI Sakamaki, Hiroshi Nakayama, Kazuya Takaku, Masanori Higeta
  • Patent number: 8549366
    Abstract: The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: October 1, 2013
    Assignee: Fujitsu Limited
    Inventors: Masanori Higeta, Kenji Suzuki, Takatsugu Sasaki
  • Patent number: 8391436
    Abstract: A receiving apparatus includes a first receiving circuit that receives an input signal based on a clock signal, and outputs a first output signal, a second receiving circuit that receives the input signal based on the clock signal, and outputs a second output signal, and a comparison circuit that compares value of the first output signal outputted by the first receiving circuit and value of the second output signal outputted by the second receiving circuit.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 5, 2013
    Assignee: Fujitsu Limited
    Inventor: Masanori Higeta
  • Patent number: 8321736
    Abstract: A transmission method for transmitting information between a transmission device and a reception device, the method includes determining whether or not an error is detected in information from the transmission device, requesting the transmission device to re-transmit the error-detected information when an error is detected, re-transmitting information corresponding to a re-transmission request as re-transmission information from the transmission device when the re-transmission request is detected, registering the re-transmission information as a test pattern, transmitting the registered test pattern to the reception device, registering the re-transmission data received from the transmission device as a collation pattern, reading out the collation pattern corresponding to the received test pattern, and collating the test pattern and the collation pattern when a test pattern is received from the transmission device, and adjusting and setting a parameter of the reception device on the basis of a pattern collatio
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: November 27, 2012
    Assignee: Fujitsu Limited
    Inventors: Masanori Higeta, Kenji Suzuki
  • Publication number: 20120239996
    Abstract: A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data.
    Type: Application
    Filed: February 22, 2012
    Publication date: September 20, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Masanori HIGETA, Hiroshi Nakayama, Hidekazu Osano, Hideyuki Sakamaki, Kazuya Takaku
  • Publication number: 20120131382
    Abstract: A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.
    Type: Application
    Filed: September 7, 2011
    Publication date: May 24, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Masanori HIGETA
  • Publication number: 20110228827
    Abstract: A receiving apparatus includes a first receiving circuit that receives an input signal based on a clock signal, and outputs a first output signal, a second receiving circuit that receives the input signal based on the clock signal, and outputs a second output signal, and a comparison circuit that compares value of the first output signal outputted by the first receiving circuit and value of the second output signal outputted by the second receiving circuit.
    Type: Application
    Filed: May 26, 2011
    Publication date: September 22, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Masanori Higeta
  • Publication number: 20100106901
    Abstract: The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.
    Type: Application
    Filed: January 6, 2010
    Publication date: April 29, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Masanori HIGETA, Kenji Suzuki, Takatsugu Sasaki
  • Publication number: 20090249152
    Abstract: A transmission method for transmitting information between a transmission device and a reception device, the method includes determining whether or not an error is detected in information from the transmission device, requesting the transmission device to re-transmit the error-detected information when an error is detected, re-transmitting information corresponding to a re-transmission request as re-transmission information from the transmission device when the re-transmission request is detected, registering the re-transmission information as a test pattern, transmitting the registered test pattern to the reception device, registering the re-transmission data received from the transmission device as a collation pattern, reading out the collation pattern corresponding to the received test pattern, and collating the test pattern and the collation pattern when a test pattern is received from the transmission device, and adjusting and setting a parameter of the reception device on the basis of a pattern collatio
    Type: Application
    Filed: March 24, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masanori HIGETA, Kenji SUZUKI