Patents by Inventor Masanori Isoda
Masanori Isoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160109915Abstract: A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.Type: ApplicationFiled: December 21, 2015Publication date: April 21, 2016Applicant: Renesas Electronics CorporationInventors: Masanori ISODA, Hidehiro FUJIWARA, Koji NII
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Patent number: 9256261Abstract: A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.Type: GrantFiled: May 28, 2013Date of Patent: February 9, 2016Assignee: Renesas Electronics CorporationInventors: Masanori Isoda, Hidehiro Fujiwara, Koji Nii
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Publication number: 20150380076Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: August 25, 2015Publication date: December 31, 2015Inventors: Noriaki MAEDA, Yoshihiro SHINOZAKI, Masanao YAMAOKA, Yasuhisa SHIMAZAKI, Masanori ISODA, Koji NII
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Patent number: 9123435Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: May 1, 2013Date of Patent: September 1, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20130326243Abstract: A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.Type: ApplicationFiled: May 28, 2013Publication date: December 5, 2013Applicant: Renesas Electronics CorporationInventors: Masanori ISODA, Hidehiro Fujiwara, Koji Nll
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Patent number: 8441843Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: October 31, 2011Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20120044775Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: October 31, 2011Publication date: February 23, 2012Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Patent number: 8076957Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.Type: GrantFiled: October 29, 2010Date of Patent: December 13, 2011Assignee: Renesas Electronics CorporationInventor: Masanori Isoda
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Patent number: 8072799Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: March 29, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20110043292Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.Type: ApplicationFiled: October 29, 2010Publication date: February 24, 2011Inventor: Masanori ISODA
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Patent number: 7843227Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.Type: GrantFiled: December 9, 2008Date of Patent: November 30, 2010Assignee: Renesas Electronics CorporationInventor: Masanori Isoda
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Publication number: 20100188887Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: March 29, 2010Publication date: July 29, 2010Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Patent number: 7715223Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: December 5, 2008Date of Patent: May 11, 2010Assignee: Renesas Technology Corp.Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nll
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Publication number: 20090146693Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.Type: ApplicationFiled: December 9, 2008Publication date: June 11, 2009Inventor: Masanori ISODA
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Publication number: 20090116279Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: December 5, 2008Publication date: May 7, 2009Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nll
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Patent number: 7477537Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: August 15, 2006Date of Patent: January 13, 2009Assignee: Renesas Technology Corp.Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Patent number: 7420834Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: August 15, 2006Date of Patent: September 2, 2008Assignee: Renesas Technology Corp.Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Patent number: 7352611Abstract: Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source wires, a plurality of static memory cells, a voltage control circuit for controlling an operation voltage applied from the power source wires to the static memory cells, a monitor circuit for monitoring a voltage of the power source wires and a mode control circuit for controlling a plurality of operation modes. The monitor circuit can detect a change of decrease of a potential difference between the pair of power source wires.Type: GrantFiled: January 19, 2007Date of Patent: April 1, 2008Assignee: Renesas Technology Corp.Inventors: Masanori Isoda, Masanao Yamaoka
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Publication number: 20070115748Abstract: Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source wires, a plurality of static memory cells, a voltage control circuit for controlling an operation voltage applied from the power source wires to the static memory cells, a monitor circuit for monitoring a voltage of the power source wires and a mode control circuit for controlling a plurality of operation modes. The monitor circuit can detect a change of decrease of a potential difference between the pair of power source wires.Type: ApplicationFiled: January 19, 2007Publication date: May 24, 2007Inventors: Masanori Isoda, Masanao Yamaoka
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Patent number: 7196960Abstract: Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source wires, a plurality of static memory cells, a voltage control circuit for controlling an operation voltage applied from the power source wires to the static memory cells, a monitor circuit for monitoring a voltage of the power source wires and a mode control circuit for controlling a plurality of operation modes. The monitor circuit can detect a change of decrease of a potential difference between the pair of power source wires.Type: GrantFiled: February 3, 2005Date of Patent: March 27, 2007Assignee: Renesas Technology Corp.Inventors: Masanori Isoda, Masanao Yamaoka