Patents by Inventor Masanori Isoda
Masanori Isoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060274571Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: August 15, 2006Publication date: December 7, 2006Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20060274572Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: August 15, 2006Publication date: December 7, 2006Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Patent number: 7113421Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: May 12, 2005Date of Patent: September 26, 2006Assignee: Renesas Technology Corp.Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20060056229Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: May 12, 2005Publication date: March 16, 2006Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20050185450Abstract: Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source wires, a plurality of static memory cells, a voltage control circuit for controlling an operation voltage applied from the power source wires to the static memory cells, a monitor circuit for monitoring a voltage of the power source wires and a mode control circuit for controlling a plurality of operation modes. The monitor circuit can detect a change of decrease of a potential difference between the pair of power source wires.Type: ApplicationFiled: February 3, 2005Publication date: August 25, 2005Inventors: Masanori Isoda, Masanao Yamaoka
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Patent number: 6781890Abstract: It is an object of the present invention to allow a voltage generating section which produces a high voltage to efficiently produce a high voltage, and to reduce a layout area of a semiconductor chip. An intermediate voltage charge pump circuit is provided in a voltage producing section of a flash memory. The intermediate voltage charge pump circuit comprises switching elements, a first charge pump circuit comprising capacitors, a second charge pump circuit comprising switching elements, capacitors and an equalizer comprising switching elements. These elements are driven by driving signals. A period during which all of one contacts of parasitic capacities Capacitor are brought into floating state temporarily is formed. After corresponding parasitic capacities are short-circuited by the switching elements, nodes thereof are electrically charged or discharged, and a high voltage is produced while reusing electric charge while using electric charge discharged to a reference potential by next cycle.Type: GrantFiled: December 3, 2002Date of Patent: August 24, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems, Co., Ltd.Inventors: Hitoshi Tanaka, Masanori Isoda, Takayuki Kawahara
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Patent number: 6667905Abstract: In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.Type: GrantFiled: January 7, 2003Date of Patent: December 23, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Chiaki Dono, Tsugio Takahashi, Hiroki Fujisawa, Masanori Isoda
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Publication number: 20030111682Abstract: It is an object of the present invention to allow a voltage generating section which produces a high voltage to efficiently produce a high voltage, and to reduce a layout area of a semiconductor chip. An intermediate voltage charge pump circuit is provided in a voltage producing section of a flash memory. The intermediate voltage charge pump circuit comprises switching elements, a first charge pump circuit comprising capacitors, a second charge pump circuit comprising switching elements, capacitors and an equalizer comprising switching elements. These elements are driven by driving signals. A period during which all of one contacts of parasitic capacities Capacitor are brought into floating state temporarily is formed. After corresponding parasitic capacities are short-circuited by the switching elements, nodes thereof are electrically charged or discharged, and a high voltage is produced while reusing electric charge while using electric charge discharged to a reference potential by next cycle.Type: ApplicationFiled: December 3, 2002Publication date: June 19, 2003Applicant: Hitachi, Ltd.Inventors: Hitoshi Tanaka, Masanori Isoda, Takayuki Kawahara
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Publication number: 20030095455Abstract: In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.Type: ApplicationFiled: January 7, 2003Publication date: May 22, 2003Inventors: Chiaki Dono, Tsugio Takahashi, Hiroki Fujisawa, Masanori Isoda
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Patent number: 6563750Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: GrantFiled: April 30, 2002Date of Patent: May 13, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
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Patent number: 6545902Abstract: Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge sharing between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.Type: GrantFiled: November 15, 2001Date of Patent: April 8, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takeshi Sakata, Tomonori Sekiguchi, Hiroki Fujisawa, Katsutaka Kimura, Masanori Isoda, Kazuhiko Kajigaya
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Patent number: 6538924Abstract: In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.Type: GrantFiled: May 30, 2001Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Chiaki Dono, Tsugio Takahashi, Hiroki Fujisawa, Masanori Isoda
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Publication number: 20020118587Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: ApplicationFiled: April 30, 2002Publication date: August 29, 2002Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
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Patent number: 6388941Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: GrantFiled: July 13, 2001Date of Patent: May 14, 2002Assignees: Hitachi, Ltd., Hitachi, ULSI Systems Co., Ltd.Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
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Publication number: 20020027799Abstract: Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge sharing between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.Type: ApplicationFiled: November 15, 2001Publication date: March 7, 2002Inventors: Takeshi Sakata, Tomonori Sekiguchi, Hiroki Fujisawa, Katsutaka Kimura, Masanori Isoda, Kazuhiko Kajigaya
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Publication number: 20020015328Abstract: In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.Type: ApplicationFiled: May 30, 2001Publication date: February 7, 2002Inventors: Chiaki Dono, Tsugio Takahashi, Hiroki Fujisawa, Masanori Isoda
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Publication number: 20020006062Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: ApplicationFiled: July 13, 2001Publication date: January 17, 2002Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda
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Patent number: 6330178Abstract: Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge sharing between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.Type: GrantFiled: April 25, 2000Date of Patent: December 11, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems, Co., Ltd.Inventors: Takeshi Sakata, Tomonori Sekiguchi, Hiroki Fujisawa, Katsutaka Kimura, Masanori Isoda, Kazuhiko Kajigaya
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Patent number: 6097623Abstract: Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge share between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.Type: GrantFiled: August 28, 1998Date of Patent: August 1, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takeshi Sakata, Tomonori Sekiguchi, Hiroki Fujisawa, Katsutaka Kimura, Masanori Isoda, Kazuhiko Kajigaya
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Patent number: 5555215Abstract: The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.Type: GrantFiled: October 5, 1995Date of Patent: September 10, 1996Assignees: Hitachi, Ltd, Hitachi ULSI Engineering CorporationInventors: Yoshinobu Nakagome, Kiyoo Itoh, Hitoshi Tanaka, Yasushi Watanabe, Eiji Kume, Masanori Isoda, Eiji Yamasaki, Tatsumi Uchigiri