Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: A power saving wireless fire alarm system has a master station and a plurality of battery-powered fire detecting cc terminals linked for wireless communication with each other. Upon detection of a fire occurrence at one of the fire detecting terminals, the fire detecting terminal transmit a fire detection message to a master station which in turn transmit a wake-up message to the other fire detecting terminals and thereafter a fire information message which starts a multiple synchronous communication between the master station and the fire detecting terminals. Each fire detecting terminal has a power controller which selects an intermittent reception mode of activating its own receiver only intermittently until receiving the wake-up message or information indicative of the fire occurrence, and select a constant operation mode thereafter to make the fire detecting terminals be ready for the multiple synchronous communication commenced by the fire information message from the master station.

Abstract: A radio communication system minimizes power consumption against noises. The system includes a first radio terminal (10A) with a first transmitter (40A) for transmitting a first data indicative of a specific event, and a second radio terminal (40A) with a battery (14B) and a receiver (20B). The first radio terminal (10A) includes a first bit interpolator (32A) which inserts a check bit pattern of “01010101” at a predetermined cycle into one frame of the first data. The second radio terminal (10B) has a second power controller (60B) which intermittently activates the second receiver (20B) at predetermined intervals in order to receive the bit-interpolated data from the first transmitter.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

Abstract: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

Abstract: A data encoding/decoding apparatus comprises a decoder which decodes a coded stream, which is formed in a first format and inputted on real time, to generate video data and audio data. A video output memory stores the video data from the decoder. An audio output memory stores the audio data from the decoder. A video input memory is provided to be connected to the decoder through a first data path when the coded stream is transcoded to generate a second stream formed in a second format. An audio input memory is provided to be connected to the decoder through a second data path when the transcoding is performed. An encoder encodes the video data from the video input memory and the audio data from the audio input memory to generate the second stream.

Abstract: A contour emphasizing circuit is provided with a number-of-pixels changing circuit (37) which changes the numbers of pixels of digital R, G, and B signals, a gamma correction circuit (39) which performs gamma correction on the output of the circuit (37), a Y-signal generating circuit (36) which generates luminance signals from the output of the circuit (37), an contour extracting circuit (38) which extracts contour components from the output of the circuit (36), a coefficient multiplying circuit (42) which outputs contour components for R, G, and B by multiplying the extracted contour components by coefficients Kr, Kg and kb contour adding circuit (34r), (34g), and (34b) which respectively add the outputs of the circuit (39 and 42). Thus, the contour emphasizing circuit performs contour emphasis on the digital R, G, and B signals.

Abstract: A PLL circuit is provided with a lock/unlock detection circuit which detects the locked or unlocked state of the PLL circuit by comparing the phases of a horizontal synchronizing signal with each other and an internal synchronizing signal generating circuit which outputs the comparison signal as an internal synchronizing signal when the locked state is detected or outputs the horizontal synchronizing signal as an internal synchronizing signal when the unlocked state is detected. Another mode of a PLL circuit is provided with a skew detecting circuit which resets a frequency dividing circuit upon detecting a skew which is deviated from a normal period in an external synchronizing signal, generates a dummy pulse upon detecting that no skew occurs in the external synchronizing signal in the normal period, and generates a reference signal in combination of the dummy pulse with the external synchronizing signal. When the skew detection circuit detects a skew, the circuit also resets a phase comparator circuit.

Abstract: A contour emphasizing circuit has a Y-signal generator (36) which generates a luminance signal from digital R, G and B signals, a contour extracting circuit (38) which extracts contour component from the generated Y signal, a factor multiplier (42) which multiplies the contour component by factors Kr, Kg and Kb and outputs contour components for R, G and B and contour adders (34r, 34g and 34b) which add the contour components for R, G and B to the R, G and B signals respectively and which emphasizes the contour for the digital R, G and B signals.

Abstract: Since A/D conversion circuits 30r, 30g and 30b to convert for output analog R, G and B signals to digital signals, a phase adjustment circuit 31 to output by delaying in the portion of 1 linc output signals of these A/D conversion circuits 30r, 30g and 30b, a first signal generation circuit 35 to generate Y signals from output signals of A/D conversion circuits 30r, 30g and 30b, a second Y signal generation circuit 37 to generate a Y signal from an output signal of the phase adjustment circuit 31, a contour extracting circuit 39 to extract a vertical contour component and a horizontal contour component from Y signals generated by first and second Y signal generation circuits, and contour adders 34r, 34g and 34b to output signals contour-emphasized adding a vertical contour component and a horizontal contour component extracted by this contour extracting circuit 39 to output signals of the phase adjustment circuit are provided, and since it has been designed that the contour extracting 39 extracts a vertical c

Abstract: A contour emphasizing circuit is provided with a Y-signal generating circuit (36) which generates luminance signals from digital R, G, and B signals, a contour extracting circuit (38) which extracts contour components from the generated Y-signal, a coefficient multiplying circuit (42) which outputs contour components for R, G, and B by multiplying the extracted contour components by coefficients Kr, Kg, and Kb, addition circuits (34r, 34g, and 34b), and a contour emphasis enabling circuit (39) which controls the period for which contour components extracted by the extracting circuit (38) arc supplied. Therefore, the contour emphasizing circuit prevents process errors in the peripheral portion of the screen of a display.

Abstract: Described herein is an interlock system for an isostatic press machine of the type including a high pressure container having upper and lower closure plugs releasably received in upper and lower openings to be used for loading and unloading work therethrough, and a holder frame for supporting the axial force of the container in an isostatic pressing phase of the press operation, the holder frame being pivotally supported at one side thereof for swinging movements about a vertical axis into and out of a holding position in engagement with the high pressure container, wherein the interlock system is provided with a lock mechanism constantly urged to lock the holder frame in the holding position, and a control means adapted to control the lock mechanism to maintain the lock on the holder frame when the internal pressure of the high pressure container is higher than a predetermined level and to release the lock when lower than the predetermined level.

Abstract: A hot isostatic press apparatus wherein a material to be processed such as preliminarily shaped metal powder is charged into a high pressure vessel provided with a heater and the material to be processed is pressed by superhigh pressure of fluid or gas sealed into the vessel and heating by a heater. The apparatus includes a main station including a high pressure vessel, a movable cover, a member for moving the material to be processed; one or more auxiliary stations including an inserting station, a preheating station, a removing station, etc.; a sealed tank; and transfer mechanisms for the material to be processed. The apparatus also includes a seal leakage detector.