Memory device, memory controller and memory system
Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-345415, filed on Dec. 22, 2006, Japanese Patent Application No. 2007-10763 filed on Jan. 19, 2007, and Japanese Patent Application No. 2007-27827, filed on Feb. 7, 2007, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Technical Field
The present invention relates to a memory device for recording two-dimensionally arrayed data including digital image data, a memory controller of the memory device, and a memory system. Particularly, the present invention relates to a memory device, memory controller and memory system for increasing an effective bandwidth indicating the number of data items that can be processed per unit time.
2. Prior Art
The market size of the memory devices for recording two-dimensionally arrayed data, like digital image data, has been gradually increasing along with the popularization of video distribution through digital broadcasting or the Internet. Digital image data is a group of data obtained by constituting gradation information of pixels using a plurality of bits (e.g., 256 gradation levels of 8 bits). For example, one frame of image data for high-definition broadcasting is constituted by 1920×1040 pixels. Each frame of this image data is arranged in an address space within image memory in accordance with a predetermined mapping method.
Such memory mapping is defined so that the most efficient access can be made, on the basis of the configuration and operation of synchronous DRAM (SDRAM) that is presently popular. For example, SDRAM has a plurality of banks, and each bank has a plurality of word lines and bit lines, a plurality of memory cells that are at the intersections of the word lines and bit lines, and sense amplifiers corresponding to the bit lines. The plurality of banks can independently execute active operation. The active operation performed in the SDRAM is a series of operations for selecting a word line and activating the corresponding sense amplifier on the basis of a row address. Further, read operation performed in the SDRAM is a series of operations for outputting a bit-line potential as read data to an input/output terminal on the basis of a column address, the bit-line potential being amplified by the sense amplifier, while write operation is a series of operations for inputting selected write data, which is inputted from the input/output memory, to a bit line that is selected based on the column address.
An address space within a memory of the SDRAM is constituted by a plurality of page areas each of which can be selected by a bank address and a row address, and each of the page areas has a group of bits or a group of bytes that can be selected by a column address. The group of bytes (or the group of bits) that are selected by the column address are inputted/outputted via a plurality of input/output terminals.
According to a generally known mapping method, a pixel of digital image data is associated with each byte (or bits) of the group of bytes (or the group of bits) that can be selected by the column address within a page area. Moreover, according to this mapping method, each of the banks of the SDRAM can independently execute the active operation and the read or write operation, thus the plurality of page areas associated with an arrangement of pixels of the digital image data are arranged so that page areas that are vertically and horizontally adjacent to each other on the image correspond to different bank addresses respectively. For example, if the SDRAM is constituted by four banks, the page areas corresponding to bank addresses BA=0, 1 are alternately arranged in the odd-numbered rows, while the page areas corresponding to bank addresses BA=2, 3 are alternately arranged in the even-numbered rows. By arranging the page areas in this manner, when reading or writing one frame of image data, different banks can execute the active operation and the read or write operation alternately and temporally overlapped, and a bandwidth, which is the number of processable pixels per a unit time, can be increased remarkably.
Patent Documents 1 and 2 describe that the access efficiency is improved by allowing simultaneous access to a plurality of rows in a semiconductor memory for storing image data.
Furthermore, Patent Document 3 describes a memory device that is provided with a sub-array selection circuit for performing control to activate, simultaneously, a sub-array allocated to an input row address and a sub-array allocated to a row address right above the input row address, in order to solve the increased reading time and power consumption since the data in every other row need to be read when using the DRAM in image expansion processing.
However, Patent Document 3 is designed to enhance the efficiency of horizontal accesses that are made continuously in a row direction of the image, and thus does not describe the rectangular access.
Moreover, Patent Document 4 describes a data processing system in which a bus controller issues an address active command, in response to an access instruction sent from a data processing section, to a storage area different from a storage area accessed in a burst mode, and thereby setting of an access address is made possible. Specifically, while the memory controller activates and accesses one bank, an active command is issued to other bank to perform active operation before hand on this bank, whereby acceleration of read/write operation can be realized.
Also, Patent Document 5 discloses an image processing device having: an image memory; and a control unit for continuously generating a column address while accessing an arbitrary bank, to continuously access an arbitrary address within the same page, and row-activating a bank to be subsequently accessed in advance and thereby immediately accessing the bank to be newly accessed even if accessed bank is switched to another bank. Specifically, there is described that the memory controller has an address order prediction circuit to predict a bank to be subsequently accessed and issue an active command to the memory.
Patent Literature 6 describes a memory system, wherein a volatile memory is provided in a plurality of banks, a refresh target bank is specified by an auto-refresh command, and, during a refresh operation performed by the refresh target bank, the banks other than the refresh target bank execute a normal memory operation in response to a normal memory operation command. However, Patent Literature 6 does not describe that a plurality of refresh counts are set beforehand to perform refresh control.
Patent Literature 7 describes a memory device in which a dual port DRAM is divided into a plurality of banks, and a data read transfer cycle is performed on one bank in synchronization with a refresh cycle performed on other banks.
Patent Literature 8 describes that the memory controller executes access control on the SDRAM with two banks to read and write-data, and performs refresh operation by issuing an active command and a pre-charge command to a bank different from the accessed bank.
Patent Literature 9 describes that in the case in which access and refresh are generated simultaneously in a DRAM with two blocks, or in the case in which access has been already generated in one block, an arbiter causes the other block to execute refresh operation, and causes the former block to execute access operation.
[Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2001-312885
[Patent Literature 2] Japanese Unexamined Patent Application Publication No. H08-180675
[Patent Literature 3] Japanese Unexamined Patent Application Publication No. H09-231745
[Patent Literature 4] Japanese Unexamined Patent Application Publication No. 2002-132577
[Patent Literature 5] Japanese Unexamined Patent Application Publication No. H10-105367
[Patent Literature 6] U.S. Patent Application Publication No. US2005/0265104A1
[Patent Literature 7] Japanese Unexamined Patent Application Publication No. H08-115594
[Patent Literature 8] Japanese Unexamined Patent Application Publication No. H09-129881
[Patent Literature 9] Japanese Unexamined Patent Application Publication No. H10-11348
The occurrence of a decrease of the effective bandwidth is not limited in the rectangular access. In a generally-used synchronous DRAM (SDRAM), in response to an auto-refresh command issued from the memory controller, refresh operation is performed in all banks in parallel on the basis of the refresh addresses of the refresh address counters that are commonly provided in the memory. For this reason, once the refresh operation is started, neither horizontal access nor rectangular access can be executed, and the access operation needs to be kept in standby until the refresh operation is ended. As a result, the effective bandwidth decreases.
An object of the present invention, therefore, is to provide a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.
DISCLOSURE OF THE INVENTIONIn order to achieve the above object, according to a first aspect of the present invention, there is provided a memory device having: a plurality of banks that respectively have memory cores including memory cell arrays and are selected by bank addresses; and a control circuit, which, in response to a background refresh command and refresh burst length information, causes the memory cores within refresh target banks to successively execute refresh operation a number of times corresponding to the refresh burst length information.
In order to achieve the above object, according to a second aspect of the present invention, there is provided a memory device that operates in response to a command sent from a memory controller, the memory device having: a plurality of banks that respectively have memory cores including memory cell arrays and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
In the second aspect of the present invention, according to a first preferred embodiment, the memory device further has: a refresh address counter that counts refresh target addresses within each of the plurality of banks or within each of a plurality of groups of the plurality of banks. Also, the control circuit has: a background refresh controller that outputs refresh control signals to the set refresh target banks in response to the background refresh command; a refresh burst length register in which the refresh burst length is set; and a core controller that is provided in each of the plurality of banks, and, in response to the background refresh control signals, causes the memory cores to execute refresh operation on the addresses of the refresh address counter a number of times corresponding to the refresh burst length set in the refresh burst length register.
In the second aspect of the present invention, according to a second preferred embodiment, a refresh block count that indicates the number of memory blocks activated simultaneously in a single refresh cycle is set by the memory controller, and the control circuit causes the refresh target banks to execute the refresh operation a number of times corresponding to the set refresh burst length, in response to the background refresh command, the refresh operation being performed for simultaneously activating the blocks for the number of the refresh block count. The refresh block count is set by a mode register in advance. Alternatively, the refresh block count is inputted and set along with the background refresh command.
In the second aspect of the present invention, according to a third preferred embodiment, the refresh burst length and the refresh block count are inputted simultaneously with the background refresh command. Alternatively, the refresh burst length and the refresh block count are inputted simultaneously with a mode register setting command. In the first case, the refresh burst length register is provided in each of the banks, and the inputted refresh burst length is set in the refresh burst length register with in the refresh target banks. Further, a refresh block count register is provided, and the refresh block count that is inputted is set in the refresh block count register. In the latter case, the refresh burst length register is provided within the mode register, and the inputted refresh burst length is set in the mode register. Similarly, the refresh block count register is provided within the mode register, and the refresh block count that is inputted is set in the mode register.
In the second aspect of the present invention, according to the third preferred embodiment, during the refresh operation executed a number of times corresponding to the refresh burst length, the core controller causes, in response to a newly inputted background refresh command, the memory cores within the refresh target banks to successively execute the refresh operation a number of times that is obtained by adding the refresh burst length to the remaining number of times of the refresh operation.
Alternatively, during the refresh operation executed a number of times corresponding to the refresh burst length, the core controller causes, in response to a newly inputted background refresh command, the memory cores within the refresh target banks to successively execute the refresh operation a number of times corresponding to the refresh burst length, regardless of the remaining number of times of the refresh operation.
Furthermore, the core controller causes, in response to a refresh-all command, the memory cores within the refresh target banks to repeatedly execute the refresh operation on the addresses of the refresh address counter as well as the remaining addresses.
In the second aspect of the present invention, according to a fourth preferred embodiment, during the refresh operation performed a number of times corresponding to the refresh burst length, the core controller causes the memory cores within the refresh target banks to stop the refresh operation, in response to a background refresh stop command. The stop control of the refresh operation is performed so as not to start a subsequent refresh operation after the memory cores within the refresh target banks end the refresh operation that is being executed.
In the second aspect of the present invention, according to a fifth preferred embodiment, on the basis of the setting of an active refresh interlock flag in the mode register, the background refresh controller supplies the background refresh control signals to banks other than an access target bank corresponding to a bank address to be inputted, in response to a normal memory operation command. Accordingly, the memory controller can execute the refresh operation on the banks other than the access target bank by issuing the normal memory operation command without issuing the background refresh command.
In order to achieve the above object, according to a third aspect of the present invention, a memory device has a plurality of banks that respectively have memory cores including memory cell arrays and are selected by bank addresses, wherein a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, and each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses. The memory device also has a control circuit that causes the memory cores within banks selected by the bank addresses to execute normal memory operation corresponding to a normal operation command in response to the normal operation command during a period of horizontal access in which the two-dimensionally arrayed data is accessed horizontally, and further causes a memory core within a refresh target bank other than the horizontal access target bank to execute refresh operation in response to a background refresh command. Moreover, during a period of rectangular access in which an arbitrary rectangular area is accessed for the two-dimensionally arrayed data, the control circuit causes the memory cores within the banks selected by the bank addresses and within banks adjacent to the selected banks, to execute the normal memory operation in response to the normal operation command, and prohibits the refresh operation during the normal memory operation.
According to the third aspect described above, the memory device performs the normal memory operation on the selected bank because the normal memory operation is repeated on a specific bank during the horizontal access period, and performs the refresh operation on the refresh target bank other than the horizontal access target bank. However, during the rectangular access period, a memory access target bank cannot be predicted, thus the refresh operation that is performed along with the normal memory operation is prohibited. Accordingly, the horizontal access can be continued even during the background refresh operation, whereby the effective bandwidth can be increased.
In order to achieve the above object, according to a fourth aspect of the present invention, the memory system has the memory device of the first and second aspects and the memory controller that supplies commands to the memory device.
In order to achieve the above object, according to a fifth aspect of the present invention, the memory controller supplies the commands, refresh bank information, and refresh burst length to the memory device of the first and second aspects.
Embodiments of the present invention are described with reference to the drawings. However, the technical field of the present invention is not limited to these embodiments, and thus covers the matters described in the patent claims and equivalents thereof.
[Memory Mapping of Image Memory, and Problems involved in the Mapping Memory]
Meanwhile, the image memory 15 is generally constituted by a high-capacity and high-speed semiconductor memory device in which an integrated circuit is formed on a semiconductor substrate such as SDRAM. Such image memory is constituted by a plurality of banks Bank 0 through 3 (four banks as shown in
According to the memory mapping 12 for the display image data, page areas 14, each of which is specified by the bank address BA and row address RA, are placed in rows and columns. As shown in an enlarged area 14E, one page area 14 has 128 memory unit areas that are specified by the column addresses CA0 through 127, and each of the memory unit areas stores the 4 bytes of data items, BY 0 through 3. The 4 bytes of data items, BY 0 through 3, are inputted/outputted via a total of 32 input/output terminals of a memory, i.e., via input/output terminals DQ 0 through 7, DQ 8 through 15, DQ 16 through 23, and DQ 24 through 31. 8-bit data of each byte corresponds to signal data of a pixel.
The memory map 12 is suitable for operating, at high speed, the image memory 15 such as the SDRAM constituted by a plurality of banks. In response to an active command provided along with both the bank address BA and the row address RA, the SDRAM performs the active operation that drives the selected word line within the selected bank, reads the data stored in a memory cell into the bit line, activates the sense amplifier associated with the bit line to amplify the bit line potential, and thereafter, in response to a read command provided along with the column address CA, performs the read operation for reading the data from the selected bit line. Alternatively, after performing the active operation the SDRAM responds to a write command provided along with the column address CA and write data, to perform the write operation for writing the write data into the selected bit line. Precharge operation using a precharge command is performed after the read operation or the write operation, and then the active operation and the read or write operation are performed again. In this manner, in the SDRAM each bank can independently perform the active operation, read operation and write operation.
According to the memory map 12 shown in
By adopting the memory mapping for allocating the page areas on an image without causing the page areas having the same bank to be adjacent to each other in the row direction or the column direction, the horizontal access that is a representative access made to the image memory, i.e., the access in which the page areas 14 are moved in the row direction and one page area is selected, can be made to the image memory, while the active operation and the read/write operation are executed simultaneously by using two banks, whereby the access efficiency can be improved. The same is true for the case where the image memory is accessed in a vertical direction.
Generally, in an image system using an image memory, the transfer rate of transferring the image memory, which is a frame memory, is set faster than the speed of image display operation, so that, while the image data read by horizontally accessing the image memory is displayed on a screen, new frame data is created by means of the rectangular access, and that frame data is continuously created and outputted. Therefore, both horizontal access and rectangular access are made in an actual image system.
In the horizontal access, scanning is performed in the horizontal direction 20, thus memory access can be made efficiently, while activating adjacent banks simultaneously. In the rectangular access, on the other hand, the position of the rectangular area 22 to be accessed is not caused to go beyond a single bank and a page area within the bank, whereby the data within the rectangular area 22 can be accessed by performing single active operation for specifying the bank address BA and the row address RA, thus efficient memory access can be performed, as with the horizontal access.
A burst length BL is set to 4 as a premise. When the active operation is performed on the page area with BA 0/RA 4 by an active command ACT 32 and an instruction is issued by a read command RD 33 to read the page area with BA 0/CA 0, four 32-bit data items are successively outputted from the input/output terminals DQ in four clock cycles after a predetermined latency (four clock in the figure). Specifically, each of the four 32-bit data items in the respective column addresses CA 0 through 3 within the page area BA 0/RA 4 is outputted four times successively. This burst operation is required to the SDRAM as a standard. The above-described operation suggests that each 4 byte (32-bit) data item of each of the column addresses CA 0 through 3 within the page area 14E enlarged in
Next, 4 bytes of data items of the page area BA 1/RA 4 are outputted by means of an active command ACT 34 and a read command RD 35. Similarly, 4 bytes of data items of the page area BA 0/RA 5 are outputted by means of an active command ACT 36 and a read command RD 37, and 4 bytes of data items of the page area BA 1/RA 5 are outputted by means of an active command ACT 38 and a read command RD 39.
At this point, when an automatic refresh command AREF 40 for specifying a row address RA 6 is generated, the SDRAM memory configuring the image memory executes a refresh operation on all incorporated banks, i.e., four banks BA 0 through 3, in parallel. Specifically, the word lines of the respective row addresses RA 6 within the respective four banks are driven simultaneously, the corresponding sense amplifiers are activated, rewriting is performed, and then the precharge operation is performed. This refresh operation is performed on four page areas 31 within the memory map 12 shown in
Since the refresh operation is performed for four banks simultaneously by means of the refresh command AREF, the horizontal access is stopped temporarily when the refresh command is generated while the horizontal access is made, thus the effective bandwidth becomes narrow. This is the problem occurring in the horizontal access.
Therefore, although the horizontal access is made relatively economically, unnecessary input/output of data occurs in the rectangular access, thus the effective bandwidth decreases.
In the horizontal access shown in
On the other hand, in the rectangular access shown in
As described above, even if the data to be accessed has the same number of bytes, in the rectangular access 24 bytes of data need to be inputted/outputted by sending the read command RD six times, but in the horizontal access 16 bytes of data may be inputted/outputted by sending the read command RD four times. Therefore, in the rectangular access that exceeds the boundary of the 4-byte area (memory unit area) 45 selected by a single column address, the effective bandwidth decreases. This is the first problem of the rectangular access.
In the case of the rectangular area 22(A), 16 bytes of data can be inputted/outputted by issuing an active command ACT (50 in the figure) once for the page area BA 1/RA 6 and a read command RD (52 in the figure) four times for the column addresses CA 6, 7, 10 and 11, as shown in the timing chart.
In the case of the rectangular area 22(B), on the other hand, 16 bytes of data cannot be inputted/outputted unless an active command ACT (54 in the figure) is issued four times for the page areas BA 3/RA 2, BA 2/RA 3, BA 1/RA 6 and BA 0/RA 7 and unless a read command RD (56 in the figure) is issued four times for the column addresses CA 127 (BA 3), CA 124 (BA 2), CA 3 (BA 1) and CA 0 (BA 0), as shown in the timing chart. Specifically, in the case where the rectangular area 22 includes adjacent page areas, the active commands ACT are issued a number of times in order to perform the active operation on different banks, and the read commands RD or write commands WR have to be issued for the column addresses within the respective banks. Therefore, the amount of data that can be accessed per unit time is reduced, and the effective bandwidth is narrowed.
In the case where the rectangular area 22(B) shown in
As described above, in the case of adopting the memory mapping, that utilizes the structural characteristics of the SDRAM, in the image memory, there are the first problem in which the horizontal access is stopped due to the occurrence of the refresh command when the horizontal access is performed, the second problem in which unnecessary input/output data is generated when the rectangular access area exceeds the boundary of the memory unit area (4-byte area) selected by a column address, and a third problem in which a plurality of bank active commands are required to be issued when the rectangular access area exceeds the boundary of the page areas specified by the bank addresses.
GENERAL DESCRIPTION OF THE PRESENT EMBODIMENTHereinafter, configurations and operations for solving these problems are described briefly.
The present embodiment is to solve the discontinuation of the access that is caused by the refresh operation, the decrease of the access efficiency that is caused by the rectangular access, and other problems, wherein, first of all, the refresh operation can be performed in the background along with an access operation at the time of the horizontal access, secondly, at the time of the rectangular access, a function of efficiently accessing an area straying from or exceeding the memory unit (4-byte area) selected by a column address is made possible, and, thirdly, a function of efficiently accessing a rectangular area exceeding the boundary of the page areas and containing a plurality of page areas is made possible.
In this case, in the rectangular access, access is generated in an arbitrary bank of the memory, while, in the horizontal access, access is generated only in a predetermined bank for a certain period of time. For example, in the horizontal access in the first row of the memory map 12, access is generated only in the banks BA 0 and 1, and no access is generated in the banks BA 2 and 3 in the second row. On the other hand, in the horizontal access in the second row, access is generated only in the banks BA 2 and 3, and no access is generated in the banks BA 0 and 1 in the first row.
Therefore, in the horizontal access 20-1, a background refresh command BREN for specifying a bank in which no access is generated for some time to come is issued before memory access is made, and information of the bank in which no access is generated, SA=2/3, is notified to the memory. Specifically, subsequent automatic refresh operation is allowed in the bank SA specified by the background refresh command BREN. Therefore, normal access is not allowed to the bank SA=2, 3 to which the refresh operation is applied.
In the horizontal access 20-1 shown in
During the period of this horizontal access 20-1, when an automatic refresh request (not shown), which is activated by the background refresh command BREN within the image memory, is issued, the refresh operation is started on the banks BA 2 and 3. However, in the horizontal access, access is generated only in the banks BA 0 and 1 and different banks can independently perform the active operation in the SDRAM, thus the horizontal access can be prevented from being disturbed and stopped by the refresh operation performed on the banks BA 2 and 3.
Next, in the rectangular access shown in
However, in the present embodiment, a read command RD (62 in the figure) is issued to the column address CA 0 (63 in the figure), and byte combination information SB (64 in the figure) on the access is supplied, whereby 4 bytes corresponding to the byte combination information SB can be automatically associated with the input/output terminal DQ. In the example described above, byte shift information SB=2, which means the bytes following 2 bytes, is specified as the byte combination information SB, whereby, out of the 4 bytes of data items of the column address CA 0, the data items of the bytes BY 2 and 3 subsequent to the 2 bytes are automatically outputted along with the data items of the first two bytes BY 0 and 1 of the 4 bytes of data items of the adjacent column address CA 1.
In the rectangular access shown in
Furthermore, when the read command RD specifying BA 2/CA 4 is issued along with the combination information SB=2, the image memory outputs 4 bytes of data constituted by 2 bytes of data of column addresses CA 4 and 5. When the read command RD specifying BA 2/CA 8 is issued along with the combination information SB=2, the image memory outputs 4 bytes of data constituted by 2 bytes of data of column addresses CA 8 and 9. When the read command RD specifying BA 2/CA 12 is issued along with the combination information SB=2, the image memory outputs 4 bytes of data constituted by 2 bytes of data of column addresses CA 12 and 13.
As a result, even if the rectangular access area 22 includes the memory unit areas (four byte areas) of the eight column addresses CA 0, 1, 4, 5, 8, 9, 12 and 13, it is only necessary to issue the read command RD to the column addresses CA 0, 4, 8 and 12 four times, and unnecessary data is not outputted to the input/output terminals, thus the access efficiency can be improved by two times.
In the horizontal access 20-2 subsequent to the rectangular access, since the page areas in the second row of the memory map 12 are accessed, thus normal access is not generated in the banks BA 0 and 1 for awhile. Therefore, as with the above explanation, SA=1 is specified along with the background refresh command BREN (65 in the figure) as the bank information SA on a bank (66 in the figure) in which the fresh operation can be performed, and the automatic refresh operation is allowed in the banks BA 0 and 1 in parallel with normal access to the subsequent banks BA 2 and 3.
As described above, the horizontal accesses 20-1 and 20-2 allow the automatic refresh operation in the background when normal access is made, but the rectangular access does not allow the automatic refresh operation in the background. As a result, in the horizontal access 20-1, the normal access operation can be performed in the banks BA 0 and 1 in parallel with the refresh operation in the banks BA 2 and 3, and in the horizontal access 20-2, the normal access operation can be performed in the banks BA 2 and 3 in parallel with the refresh operation in the banks BA 0 and 1. Accordingly, the horizontal accesses can be prevented from being disturbed by the refresh operation, and the effective bandwidth can be prevented from decreasing.
Furthermore, in the rectangular access, the background refresh operation is prohibited. Accordingly, the rectangular access made to an arbitrary area can be prevented from being stopped by the refresh operation. Therefore, the effective bandwidth can be totally prevented from decreasing.
Also, in the rectangular access, the byte combination information SB is specified along with the read command, whereby combined byte data, which is obtained by combining arbitrary bytes with a column address CA of the read command as a start area, can be outputted to the 4 bytes of input/output terminals DQ. The byte combination information SB can also be specified along with a command for setting a mode register in advance of the active command.
As with
In the example of the rectangular access shown in FIG. 7, address information items BA 3 and RA 2 (71 in the figure) for specifying the page areas in the upper left section are issued along with an active command ACT (70 in the figure), and at the same time the multi-bank information SA′=0-3 (72 in the figure) is issued. In response to this, the image memory, performs the active operation on four banks BA 3, BA 2, BA 1 and BA 0 simultaneously, the four banks being specified by the multi-bank information SA′, placing a bank BA 3 of the upper-left page area in front and sequentially outputs 4 bytes of data items of the banks BA/columns CA that are specified by the subsequent four read commands RD. The same applies to the write command. In the figure, BA 3/CA 127, BA 2/CA 124, BA 1/CA 3, and BA 0/CA 0 are supplied in response to the four read commands, and 4 bytes of data items of these memory areas are outputted.
If the multi-bank information SA′ indicates “two banks in the lateral direction”, a bank on the right side of an upper left bank corresponding to the bank address BA supplied by the active command ACT is also subjected to the active operation simultaneously. If the multi-bank information SA′ indicates “two banks in the vertical direction”, a bank that is located below the upper left bank is also subjected to the active operation simultaneously. Similarly, if the multi-bank information SA′ indicates “four banks in the lateral and vertical directions”, four banks that are located on the right side, below, and on the lower right side of the upper left bank are also subjected to the active operation simultaneously. Therefore, in order to perform the active operation automatically on multiple banks, it is preferred to previously set, in the register or the like, information indicating how the row addresses RA in the respective rows of the memory map are arranged, or indicating, specifically, in what unit the row addresses RA are wrapped (row address step information).
In the rectangular access method shown in
The image processing chip 80 has: an image processing controller 81 for performing image processing, such as an encoder or decoder that responds to image compression and expansion of, for example, MPEG; and a memory controller 82 for controlling an access to the image memory chip 86 in response to a memory access request that includes image area specification issued from the image processing controller 81. The memory controller 82 has: a background refresh controller 84 for controlling the background refresh operation in the horizontal access; a byte boundary controller 85 for controlling an access to an arbitrary combination of bytes in the memory unit area (4-byte area) in the rectangular access; and a multi-bank activating controller 83 for controlling accesses to a plurality of areas in the rectangular access. By performing these control operations, commands required in each operation, bank addresses, row addresses, column addresses, byte combination information SB, refresh bank information SA, multi-bank information SA′ and the like are issued to the image memory 86.
The image memory 86 has a plurality of banks Bank 0 through 3 within memory core 92, and further has a row controller 87 for controlling mainly the active operation, a column controller 90 for controlling the read or write operation, and a background refresh controller 89, there controllers performing control with respect to the memory core 92. The row controller 87 has a multi-bank activation controller 88, and the column controller 90 has a byte boundary controller 91. A row decoder RowDec, column decoder ColDec, memory area MA, sense amplifier group SA, and input/output unit 93 for associating the memory area MA with the input/output terminals DQ are provided in each of the banks Bank 0 through 3.
It should be noted that the terminals SB, SA′ and SA, that are required in the abovementioned byte boundary function, a multi-bank access function, and the background refresh function, can be realized using a common special pin. These information items are supplied along with different commands, thus input data at special pin may be set to a corresponding register in response to the supplied commands.
Also, these terminals SB, SA′ and SA can be realized using unused terminals. For example, in the case where row addresses are inputted at address terminals Add 0 through 12 and column addresses are inputted at the address terminals Add 0 through 9, the address terminals Add 10 through 12 are not used when the column addresses are inputted. Therefore, control data SB, SA′ and SA can be inputted from the address terminals Add 10 through 12 that are not used when inputting the column addresses.
The group of external terminals 93 are connected to internal circuits via buffers 94 respectively. The abovementioned group of commands is inputted to a command controller 95, and control signals corresponding to the commands are supplied to the internal circuits. Also, in response to a mode register set command, the command controller 95 sets a predetermined set value to a mode register 96 on the basis of a set data supplied to an address pin Add. The set information that is set by the mode register 96 is supplied to the internal circuits. The row controller 87 has the multi-bank activation controller 88 and a row address calculator 97 required for multi-bank activation. An active pulse is supplied from the multi-bank activation controller 88 to a bank to be activated. Furthermore, a row address to be activated is supplied from the row address calculator 97 to each bank. The bank Bank is provided with a refresh row address designator 98 that designates a row address to be refreshed within the bank. The refresh row address designator 98 has, for example, a refresh counter for generating a row address required when automatically generating a refresh command. The internal configuration of the bank is as explained above.
Hereinafter, image memory and memory controller are described in detail with reference to the byte boundary function, multi-bank active function, background refresh function illustrated in
<<Byte Boundary>>
On the other hand,
Then, the input/output unit of the image memory extracts a total of 4 bytes out of byte data corresponding to a different column address CA within a page, on the basis of byte combination information consisting of the first and second information, and associates the 4 bytes with the input/output terminals DQ 0 through 31. Then, required 4-byte data is inputted/outputted once from 32 bit input/output terminals DQ.
The image memory associates 2-byte data (BY 2, 3), which is the second half of the 4-byte area selected by a column address CA=1, with 2-byte data (BY 0, 1), which is the first half of the 4-byte area selected by a column address CA=2, in a manner shown by DQ 16-23, DQ 24-31, DQ 0-7, and DQ 8-15, on the basis of the byte combination information SB=2 and BMR=UP. This association is performed in the input/output unit 93 by the byte boundary controller 91 shown in
In
“0 through 3”, which indicate 4 bits within a 4-bit area selected by a row address RA and a column address CA, are shown within each of the memory logical spaces 15-1 and 15-2, and correspond to the input/output terminals DQ 0 through 3 respectively. Also, “0 through 3”, which indicate 4 bits within each memory logical space corresponding to the pixels of the image, are shown in each of the memory mappings 12-1 and 12-2 on the left side. Specifically, the memory mapping shows how each pixel of the image is associated with each of the input/output terminals DQ 0 through 3 of the memory.
In the image system, a system designer can freely associate an image pixel with any of the 4 bit input/output terminal DQ 0 through 3 that are simultaneously accessed using certain addresses BA, RA and CA. The mapping 12-1 is an example of mapping four pixels arranged from left to right in the figure onto the input/output terminals DQ 0 through 3 arranged in the same direction as the incrementing direction of the addresses (from left to right), and this mapping is called “big endian”. On the other hand, the mapping 12-2 is an example of mapping four pixels onto the input/output terminals DQ 3 through 0 arranged in the direction opposite to the incrementing direction of the addresses, and this mapping is called “little endian”.
In mapping 12-1 and mapping 12-2, the rectangular access is generated in four pixels 123 and 127 between the 6th pixel to the 9th pixel on the upper left corner of the image. However, such mapping is performed in the direction opposite to that of 4 bits within the memory, thus different accesses are required. Specifically, in the case of the mapping 12-1, it is necessary to input/output data with respect to the pixels arranged from left to right in the image, in order of DQ1 within CA=1, DQ2 within CA=1, DQ3 within CA=1, and DQ0 within CA=2, as shown by the arrow 120. In the case of the mapping 12-2, on the other hand, it is necessary to input/output data with respect to the pixels arranged from left to right in the image, in order of DQ2 within CA=1, DQ1 within CA=1, DQ0 within CA=1, and DQ3 within CA=2, as shown by the arrow 124.
The bit combination information items SB, BMR are set in order to respond to such different types of mapping. Specifically, in the case of the mapping 12-1, as shown by 121 in the figure, a starting address constituted by BA=0 and CA=1 and bit combination information constituted by SB=1 and BMR=UP are issued along with a read command RD, and, in response to this issuance, 3 bits of CA=1, i.e., DQ 1, 2 and 3, and DQ 0 of CA=2 are simultaneously outputted as shown by 122 in the figure.
In the case of the mapping 12-2, on the other hand, as shown by 125 in the figure, a starting address constituted by BA=0 and CA=1 and bit combination information constituted by SB=1 and BMR=DOWN are issued along with a read command RD, and, in response to this issuance, 3 bits of CA=1, i.e., DQ0, 1 and 2, and DQ 3 of CA=2 are simultaneously outputted as shown by 126 in the figure.
In this manner, the bit combination information SB and BMR are specified in accordance with the different memory mappings such as big endian and little endian, whereby the image memory can input/output 4 bits simultaneously in response to the memory mapping on the system side. By increasing the types of such bit combination information, a flexible 4 bit access can be realized on various mapping types.
Pixel positions (X 0 through X 11) in the screen indicate physical positions on the same screen. “Information on each pixel” that each pixel position has is designated as “A” through “L” in both systems, and this means that both systems display the same image.
In the big endian system, the pixel positions X 0 through 3 are associated with DQ 0 through 3 of address CA 0 of the memory, the pixel positions X 4 through 7 are associated with DQ 0 through 3 of address CA 1 of the memory, and the pixel positions X 8 through 11 are associated with DQ 0 through 3 of address CA 2 of the memory.
In the little endian system, on the other hand, the pixel positions X 0 through 3 are associated with DQ 3 through 0 of the address CA 0 of the memory, the pixel positions X 4 through 7 are associated with DQ 3 through 0 of the address CA 1 of the memory, and the pixel positions X 8 through 11 are associated with DQ 3 through 0 of the address CA 2 of the memory.
Specifically, when comparing the both systems, the relationship between each of the pixels X 0 through 3 within the image processing system and each of the input/output terminals T 0 through 3 in the big endian is opposite to that in the little endian. Therefore, the pixel information “A” of the pixel position X0 is stored in the physical positions (DQ 0 of CA0 and DQ3 of CA0) of different memory cells in the big endian system and the little endian system.
Here, in the case where the image processing system generates a rectangular access (130 in the figure) to pixel information “F-G-H-I” of the pixel positions X 5 through 8, the memory has to access the physical positions 132 and 134 of different memory cells in the big endian system and the little endian system. Therefore, the minimum amount of information items that are required to be supplied to the memory are three information items, i.e., the information BMR on whether the system is the big endian (Up) or the little endian (Down), the address CA having a bit as a starting point, and the positional information SB of the bit which is the starting point within an address.
The big endian and the little endian are the same when the memory unit area that is accessed with the addresses RA, CA is a 4-byte area (byte group).
In the figure, the memory mappings 12 on the left side each shows which bit of the memory is allocated to each pixel within a frame image. In this example, one pixel is constituted by 2 bits of information. For example, an even-numbered bit holds data on luminance, while an odd-numbered bit holds data on a color difference.
Grouping-1 means a rectangular access that collects only the luminance information (even-numbered bits) of pixels from the second pixel through the fifth pixel, and Grouping-2 means a rectangular access that collects only the color difference information (odd-numbered bits) of pixels from the second pixel to the fifth pixel on the upper left corner. In this case, although both Grouping-1/2 are rectangular accesses made to the second pixel through the fifth pixel on the upper left corner of the image, the accesses from the image processing system to the memory and the input/output terminals DQ that are shown in the timing charts are as follows, due to the difference between the luminance (even-numbered bits) shown by the arrow 140 and the color difference (odd-numbered bits) shown by the arrow 144.
Grouping-1: DQ 0 of CA=1, DQ 0 of CA=2, DQ 2 of CA=0, and DQ 2 of CA=1 are associated with the input/output terminals DQ 0 through 3 respectively (142 in the figure), with respect to the access with CA=0/SB=2, BMR=AL (designation for collecting 4 bits every other bit) (141 in the figure).
Grouping-2: DQ 1 of CA=2, DQ 1, 3 of CA=1, and DQ 3 of CA=0 are associated with the input/output terminals DQ 0 through 3 respectively (146 in the figure), with respect to the access with CA=0/SB=3, BMR=AL (designation for collecting 4 bits every other bit) (145 in the figure).
In this manner, the same DQs (DQ0 and DQ2 in Grouping-1, for example) are accessed simultaneously within the 4-bit area of different column addresses, thus the input/output units for transferring the data to the input/output terminals DQ need to perform processing of switching the terminals for some data, i.e., processing of using a data bus of a different DQ.
The pixel positions (X 0 through 5) on the screen indicate the same physical positions on the screen on both right and left. The pixel positions hold “A, C, E, G, I, K” respectively as “luminance information”, and “B, D, F, H, J, L” respectively as “color difference information”.
Here, in the case where the image processing system generates a rectangular access 151 to the luminance information “C-E-G-I” of the pixel positions X 1 through 4, the memory has to access only the even-numbered DQs (153 in the figure) as shown in
The minimum information items that the memory needs to receive in order to make such accesses are three information items, i.e., information indicating whether the system adopts a method of holding the luminance information in the even-numbered DQs and the color difference information on the odd-numbered DQs (whether access needs to be made every other DQ) (BMR=AL), the address having a bit as a starting point (CA), and position information (SB) of the bit which is the starting point in the 4-bit area of the address. The column address CA and bit combination information SB and BMR are already explained in
In this case, since the same DQs (DQ0 and DQ2 in Grouping-1, for example) are accessed with different addresses, the input/output unit for transferring the data to the input/output terminals needs to perform the processing of switching the terminals so as to use the data bus of a different DQ. Therefore, a plurality of switches shown by white circles and black circles are provided in the memory, and these switches are controlled based on the above-described information SB and MBR.
In
The abovementioned second information BMR=V can have various information on the big endian (V=UP), little endian (V=DOWN), and the cases where the luminance information is stored in the even-numbered DQs and the color difference information is stored in the odd-numbered DQs (V=AL).
The image system can realize the byte boundary functions in the rectangular access in any methods of (A) and (B) of
As described above, in the timing chart (A), a read command RD or a write command WT, which is not shown, is supplied simultaneously with the byte combination information SB and BMR (166 in the figure). Also, in the timing chart (B), a mode register set command EMRS (167 in the figure) is supplied simultaneously with the second information BMR, and the read command RD or the write command WT, which is not shown, is supplied simultaneously with the first information SB.
In the example shown in
In this manner, the bit boundary or byte boundary functions can be realized even in the case where the width of the input/output terminals DQ is 4 bits or 32 bits (4 bytes).
In the example shown in
Specifically, in the case where the memory mapping on the system side is designed for the little endian, the switching means 190 is provided to switch the input/output terminals 0 through 3 in the image memory 86 to 3 through 0 in the memory controller 82. As a result, to the image memory, the system side appears to respond to the big endian. Therefore, even if the system is configured to have a memory only for the second information BMR=UP, the byte boundary functions for the little endian can be realized.
In FIG. 20(1), in the case where an access is made in units of addresses (A), the pixel positions (X 0 through 7) on the screen are associated one-on-one with addresses (CA) on the memory side (X 0 through 3 and CA=0, X 4 through 7 and CA=1), thus there is no problem. However, in the case where a signal SB is specified to make an access in units of bits (B), a shift in the pixel positions (X 1 through 4 (BCDE), 200 in the figure) does not match with a shift in the physical positions of memory cells (CBAH, 201 in the figure) in the memory where the only bit boundary functions (BMR=UP only) corresponding to the big endian exists, thus wrong data CBAH is transferred. In this case, the BCDE on the memory cells can be outputted by means of the bit boundary functions (BMR=DOWN) corresponding to the little endian. However, if the bit boundary functions that are capable of responding to both the big endian and the little endian are provided in the memory, increase in costs is caused.
Therefore, as shown in FIG. 20(2), the connecting unit 190 for cross-connecting the input/output terminals on the system side and the memory side is provided so that the pixels X 0 through 3 on the image correspond to the DQ 0 through 3 on the memory cells, whereby the image processing system 80 for little endian appears to the memory 86 to be a system for big endian. Accordingly, the shift 200 of the pixel positions matches with the shift 202 of the physical positions of the memory cells, and thereby normal data BCDE can be transferred even if an access is made while shifting bits so as to respond to the big endian.
As described above, by using the connecting unit 190 capable of performing cross-conversion to switch the terminals connecting the system and the memory, even in the case of the memory having the bit boundary (or byte boundary) functions for big endian, the bit boundary (or byte boundary) functions can be realized in the image processing system for little endian. Moreover, in the case of the memory having the bit boundary (byte boundary) functions for both big endian and little endian, the memory and the system may be connected to each other via the connecting unit 200 that makes connection without switching the terminals.
The arbitrary number of bits (Nb) described above means concept including both bit units and byte units, and Nb=8 (1 byte) is set according to the above-described embodiment. Also, the multiple number (N) explains that data items of many times of the arbitrary number of bits (Nb) are accessed from one address, and Nb×N corresponds to the number of input/output terminals. N=4 is set according to the above-described embodiment, thus the multiple number corresponds to the input/output terminals, the number of which is equivalent to 4 bytes. More concretely, the number of input/output terminals is Nb×N, thus the number of input/output terminals=32 (=8×4).
Also, Ng indicating the plurality (Ng) of bit groups is the number of groups of all bits or bytes (groups of Nb bits) that the memory has, and is equivalent to the number obtained by dividing the capacity of the entire storage area by Nb. Normally, the number of Ng is much larger than the multiple number (N) that is the number of bit groups inputted/outputted at once. For example, in the case of a 64 M-bit memory, if Nb=1, Ng=64M, and if Nb=8, Ng=8M. According to the previous examples, when considering the 64 M-bit memory, if Nb=8, Ng=8M. According to the previous examples, the address information that can select any one bit group is information (SB) indicating a bit which is a starting point of an address (BA, RA, CA), wherein data that is narrowed down to 4 bytes by the address (BA, RA, CA) is limited to a byte as a starting point by the information (SB) indicating a byte as a starting point.
Selecting the same number of bit groups as the multiple number (N) in accordance with a rule means that, according to the previous examples, a plurality of bytes are selected in accordance with the information on a combination of bytes (BMR) that are selected simultaneously with a start byte. Since N=4, when BMR=Up, 4 bytes that continue in the Up direction can be accessed simultaneously from an arbitrary byte.
The image processing system accesses, via 32-bit (=Nb×N) input/output terminals, 4 bytes that are selected by the information capable of selecting any one bit group (1 byte according to the previous examples) (BA, RA, CA), the information on a byte that is a starting point (SB), and the information on a combination of bytes (BMR) that are accessed simultaneously.
The amount of memory of a memory device shown in
If the address is incremented by one bit in the same 64 bit memory, the number of bit groups with a bit unit of 4 (Nb=4) is 16 (Ng=16), and if the input/output terminals remain Nb×N=32, the predetermined multiple number becomes 8 (N=8), thus seven other bit groups are selected by the combination information BMR.
[Memory with Byte Boundary Functions]
The configuration of the image memory having the byte boundary functions is described next in detail. According to the byte boundary functions, 4 bytes of data beyond a memory unit area (4-byte area) can be selected, the memory unit area being selected by the column address. Therefore, functions for inputting/outputting 4-byte to be required data are added to the memory. Hereinafter, for simplification, there is described an example in which only the first information SB (referred to as “start byte” or “start bit”) is provided as the byte combination information. The second information BMR is an example of UP only.
[Example of Internal Column Control]
First of all, several specific examples of column control performed on the inside of the memory are described.
As shown in
The memory bank 92 is divided into byte areas 0 through 3, which are four memory blocks. Each byte area has a memory cell array 224, a second amplifier 225, a pair of data latches 226 and 227, and a data bus switch 228, and inputs/outputs one byte (8 bits) of data at one access. A total of 32 bits (4 bytes) of data are inputted/outputted to an I/O bus from the four byte areas. The I/O bus is connected to 32 bits of input/output terminals DQ 0 through 31 via buffers. It should be noted that
The column controller 90 has a column timing controller 220 for controlling the timing for operating the column decoder 222, and a data latch selector 221 for controlling the data latch circuits 226 and 227 and the data bus switch 228. The data latch selector 221 controls the data latch circuits 226 and 227 and data bus switch 228 within each of the byte areas 0 through 3 in response to a column address CA and a start byte SB.
As shown in
The memory chip 86 shown in
The right side of
Specifically, the column decoder selects column lines (bit lines) equivalent to one byte in each byte area at one access. When the read operation is performed, data equivalent to 1 bytes are selected from the memory cell array 224 of each byte area, are then amplified by the second amplifier 225 and cached to the data latch circuits 226 and 227. At this moment, memory cells that are mapped by the same column address CA are accessed in each byte area. In order to realize a byte boundary access made across the boundaries of the memory unit areas (four byte areas) that can be selected by the column address, the column decoder 222 selects a column line again after ending the first access. The address of this column line is CA 1, which is an address after the previous address CA 0. 1 byte of data that is read from the memory cell array 224 is amplified by the second amplifier, and cached to the data latch circuit 227 different from the first access.
Therefore, 8 bytes of data items, which are twice as large as the 4-byte data required by the input/output terminals DQ in one access, are present in the data latch circuits 226 and 227, thus the data bus switch 228 selects 1 byte of data, i.e., half data, from 2-byte data cached to the data latch circuits of each byte area, and transfers this data to the I/O bus. The data latch selector 221 controls cache operation on the data latch circuits 226 and 226 within each byte area and switching operation on the data bus switch 228, in response to the column address CA0 and the start byte signal SB=1. Accordingly, byte data corresponding to different column address CA 0 and CA 1 can be transferred from each byte area to the I/O bus.
As a result, as shown in
The configuration shown in
In the case of a write command, the 4-byte data that is supplied to the input/output terminals DQ is stored into the two data latch circuits 226 or 226 via the data bus switch 228 that is switched and controlled in response to the column address CA and the start byte signal SB, and then written to the two memory cell arrays 224-0 or 224-1.
In
In the next clock cycle, the column decoder 222 issues decode signals 222D0 and 222D1 corresponding to column address CA 4 and CA 5, and further caches 8 bytes of data Q16 through Q23 to the data latch circuits. Then, the data bus switch 228 transfers 4 bytes of data Q 09 through 12. In the next clock cycle, the data bus switch 228 transfers 4 bytes of data Q 13 through 16 to the input/output bus. At this moment, it is not necessary to cache new 8-byte data from the memory cell arrays.
As with the above explanation, the write operation is performed such that, if the burst length BL is 4, 4 bytes of data are supplied to the input/output terminals DQ in four cycles, and then stored in the data latch circuits 226 and 227 via the data bus switch 228. Then, in response to the decode signals of the column addresses CA 0, 1, CA 2, 3, and CA 4, 5 from the column decoder 222, a total of 16 bytes of data are written to the memory cell arrays in three cycles.
Specifically, 8 bytes of data Q 00 through 07 are cached first, and thereafter 4 bytes of data Q 08 through 11, Q 12 through 15, and Q 16 through 19 are cached to the data latch circuits. Then, the data bus switch 228 transfers the 4 bytes of data DQ 1 through 4, Q 05 through 08, Q 09 through 12, and Q 13 through 16 to be transferred, to the input/output bus sequentially. In this case as well, the selected signal S221 of the data latch selector 221 consists of 8 bits (2 bits in each byte area). As described above, in the read operation, the memory cell arrays cache the data to the data latch circuits in four cycles by means of the decode signals of the column addresses, and the data transfer operation with respect to the input/output bus from the data latch circuits is also performed in four cycles.
In the case of writing operation as well, 4 bytes of data are supplied to the input/output terminals DQ in four cycles, and stored in the data latch circuits 226 and 227 via the data bus switch 228 in four cycles. Thereafter, in response to the decode signals of the column addresses CA 0/1, CA 2, CA 3 and CA 4 from the column decoder 222, a total of 16 bytes of data are written to the memory cell arrays in four cycles.
Since the input/output rate is doubled in this manner, it is necessary to double the amount of data in the memory that needs to be cached. In the example shown in
In order to enable such collective caching of the 16-byte data as shown in
It should be noted that the example shown in
Moreover, in the next clock cycle, the column decoder 222 issues internal decode signals of column addresses CA 4 through 7 to the four memory cell arrays, and further caches 4 bytes of data to the four data latch circuits. Accordingly, 16 bytes of data Q 16 through 31 are latched to the data latch circuits, and selected 4 bytes of data out of the 16 bytes of data, i.e., Q 13 through 16, and 4 bytes of data Q 17 through 20 are outputted at the rising edge and the trailing edge of the clock respectively.
In the write operation, write data is written in a direction opposite to the above-described direction into the memory cell arrays from the input/output terminals DQ via the data latch circuits.
In the case of
As shown in
Therefore, the read operation and write operation shown in
As shown in
According to
As described above, in the third example shown in
In the read operation, 1-byte data corresponding to a column address provided from the column decoder 222 in each byte area is outputted to the data latch circuit 226, and then transferred to the input/output terminals DQ via the data bus switch 228. In the write operation, the 4-byte data that is inputted to the input/output terminals DQ is latched to the data latch circuit 226 via the data bus switch 228 in each byte area. Thereafter, the latched data is written to a memory corresponding to the column address from the column decoder 222 in each byte area.
In the case where the memory unit area selected by a column address is constituted by 4 bits, the four byte areas within the bank shown in
[Control of Relationship with Input/Output Terminals]
Next, there is described an example of control of a relation between the input/output terminals DQ within the image memory and a bus or data latch circuit within the memory cell array.
In the case where the input/output terminals DQ are not switched around, data that is stored as the data of Byte 1 is outputted to the DQ terminal corresponding to Byte 1, without depending on the start byte signal SB. Therefore, connections between the memory cell array 224 and input/output buffers 94I/O are always fixedly allocated. Therefore, designation of the start byte signal SB is performed for simply determining which bus of the column address CA in the memory cell array 224 should be connected to the input/output butter 94I/O.
The example shown in
In this manner, if the input/output terminals DQ are not switched around, the data Q 01 that is outputted from Byte 1 Area of the memory cell is definitely connected to the input/output terminal DQ[15:8] corresponding to Byte 1 of the input/output buffer 94I/O. Therefore, the control of the data bus switch 228 using the byte start signal SB means control of connecting the input/output buffers 94I/O to either one of the data latch circuits of an area corresponding to the two column addresses CA.
The data bus switches 228 within the respective four byte areas 0 through 3 shown in
As is clear from
In this manner, the input/output terminals DQ are switched around with respect to the busses or data latch circuits within the memory cell array according to the start byte signal SB. Specifically, the byte data Q 01 that is outputted from the byte area Byte 1 within the memory cell array is connected to the DQ[7:0] corresponding to Byte 0 of the input/output buffer 94I/O when SB=“1”, and is also connected to DQ[15:8] if SB=“0”. The byte data Q05 of the byte area Byte 1 is connected to DQ[23:16] when SB=“3”, and is also connected to DQ[31:24] when SB=“2”. Specifically, the positions of the four switches in the closed state as shown in
Next, control of a relation between the big endian and little endian is described with reference to the control of the relation with the input/output terminals.
In the figure, the mode register 96 is provided with the second information BMR as the byte combination information indicating the up mode or down mode, and the mode is set to either one of the modes. However, the memory core 350 having the column decoder, memory cell array, and second amplifier that are shown in
On the other hand,
In the example in
For example, when the column address CA 0 and start byte SB=1 as shown in
In this manner, the column address to be provided to the four byte areas Byte 0 through 3 within the respective memory cores are switched around by the column shifter 291 in accordance with the up mode or down mode. Then, a combination of column addresses, which is uniquely determined by the start byte signal SB and the mode signal BMR, is supplied to each byte area of each memory core 350 via the column shifter 291. This column shifter 291 selects one of the two column addresses required to be switched around, in accordance with the up mode/down mode Up/Down, the two column addresses being selected from four column addresses caby0z through caby3z from a column address controller 90A. Specifically, in the byte area Byte 0, either cabyoz or caby3z is selected. In the byte area Byte 1, either caby1z or caby2z is selected. In the byte area Byte 2, either caby1z or caby2z is selected. Also, in the byte area Byte 3, either caby0z or caby3z is selected.
In the case of a single data rate (SDR), 4 bytes of data is only able to be accessed at one access, thus, as described with reference to
In the case of a double data rate (DDR), on the other hand, 4 bytes of 8-byte data need to be inputted/outputted at one access. Therefore, in the configuration shown in
As shown in
As described above, in the case of the DDR memory, each byte area within the memory cell array has the block of even column addresses (CA[0]=0) and a block of odd column addresses (CA[0]=1), then a controlled combination of column addresses caby is supplied to these blocks, and a controlled combination of column addresses for switching the data buses, daby, is supplied to the data bus switch 228.
Specifically, CA 1 is inputted as a base column address CA. Along with this input, the column addresses CA that are supplied to the even block (CA[0]=“0”) and odd block (CA[0]=“1”) within each of the byte areas Byte 0 through 3 are controlled. A column line of the column address CA 2 is activated in the area of the even block (CA[0]=“0”). A column line of the column address CA 3 is activated in the byte area Byte 0, and column lines of the column addresses CA 1 are activated in the byte areas Bytes 1, 2 and 3 in the area of the odd block (CA[0]=“1”).
As a result, the data items Q 05 through 12 are outputted to the core buses of the memory cores. Specifically, the data items Q 08 through 11 are outputted to the core buses of the even block, and the data items Q 5 through 7 and also Q 12 are outputted to the core buses of the odd block.
In the DDR memory, it is necessary to transfer 4 bytes of data from this 8-byte data to the I/O bus. Here, on the basis of the start byte signal SB and the column address CA, the data bus switch selects the data of the even block (CA[0]=“0”) in the byte area Byte 0 only. As a result, the data items Q 05 through 08 can be outputted to the input/output terminals DQ.
Here, in each of even block area and odd block area (CA[0]=“0”/“1”), the internal column address cabyaz selects caby0z, an internal column address cabybz selects caby1z, cabycz selects caby2z, and cabydz selects caby3z. Similarly, in each of even block area and odd block area (CA[0]=“0”/“1”), the column address for data bus, dabyaz, selects daby0z. Similarly, dabybz selects daby1z, dabycz selects daby2z, and dabydz selects daby3z.
In this case, CA 1 is inputted as the base column address CA. Along with this input, the column addresses CA that are supplied to the even block (CA[0]=“0”) and odd block (CA[0]=“1”) within each of the byte areas Byte 0 through 3 are controlled. A column line of the column address CA 2 is activated in the even block (CA[0]=“0”). A column line of the column address CA 3 is activated in the byte area Byte 3, and column lines of the column addresses CA 1 are activated in the byte areas Bytes 2, 1 and 0 in the odd block (CA[0]=“1”).
As a result, the data items Q 05 through 12 are outputted to the core buses of the memory cores. Specifically, the data items Q 08 through 11 are outputted to the core buses of the even block, and the data items Q 5 through 7 and also Q 12 are outputted to the core buses of the odd block.
In the DDR memory, it is necessary to transfer 4 bytes of data from this 8-byte data to the I/O bus. Here, on the basis of the start byte signal SB and the column address CA, the data bus switch selects the data Q 08 of the even block (CA[0]=“0”) in the byte area Byte 3 only, and selects the data items Q 05 through 07 from the odd block for the rest of the byte areas. Accordingly, 4 bytes of data items Q 05 through 08 can be outputted to the input/output terminals DQ.
Here, in each of even block area and odd block area (CA[0]=“0”/“1”), the internal column address cabyaz selects caby3z, an internal column address cabybz selects caby2z, cabycz selects caby1z, and cabydz selects cabyoz. Similarly, in each of even block area and odd block area (CA[0]=“0”/“1”), the column address for data bus, dabyaz selects daby3z. Similarly, dabybz selects daby2z, dabycz selects daby1z, and dabydz selects daby0z.
As described above, when comparing the down mode shown in
In this case, the relationship between the start byte SB and the shift value SV changes in the up mode and the down mode in accordance with the two modes of the endian. Specifically, in the case of the up mode, since the byte data items are arranged in the manner of Byte 0 through 3, SB and SV are the same. However, in the case of the down mode, the byte data items are arranged in the manner of Byte 3 through 0, thus SB and SV are different and in an opposite relationship.
Therefore, in the case where the image memory has a start byte signal SB terminal only and the internal structure is controlled in accordance with the shift value SV, it is necessary to non-invert or invert the start byte signal SB so as to obtain the shift value SV depending on whether the mode is the up mode or down mode. The same is true for the case where the image memory has a shift value SV terminal only and the internal structure is controlled in accordance with the start byte SB.
[Column Address Control in Rectangular Access]
As shown in
By this mapping of wrapping the memory unit area selected by the column address at a predetermined wrap width, efficiency of a rectangular access that is made frequently in the image memory can be improved. Specifically, while a page area is subjected to active operation by an active command, a read command and a write command are repeatedly issued in accordance with a rectangular area to be accessed, whereby an access can be made to the rectangular area within the same page area. Since an access can be made to the rectangular area within the same page area by performing the active operation once, an efficient access can be made.
As shown in
Explanation is provided with reference to the timing chart shown in
An internal column address caz[7:0] that is issued for the first access is CA=#0B/#0C, as shown in
The configuration of the image memory corresponding to this automatic rectangular access is as shown in, for example,
In the above example, the rectangular width Rwidth at the time of rectangular access is supplied along with the read command, but the rectangular width Rwidth may be set beforehand by means of the mode register set command in the mode register. Alternatively, the rectangle size BL and rectangular width Rwidth may be supplied along with the read command. The wrap width CAWrap of the column address is set by the image system beforehand, thus it is preferred that the wrap width CAWrap is set by means of the mode register set command.
In this manner, in the case of the rectangular access, if the column address CA as a starting point, the rectangular width Rwidth, and the rectangle size (BL) are provided, an internal column address to be accessed can be generated automatically on the basis of the wrap width CAWrap of the column address that is set beforehand. Therefore, the rectangular access can be made by issuing a read command once.
[Byte Boundary Functions of Page Area Boundary]
The byte boundary functions can efficiently access predetermined bytes (4 bytes) of data across the boundary of a memory unit area (4-byte area) selected by a column address. However, in the case of performing a rectangular access across a page area boundary, adjacent page areas need to be subjected to the active operation again by means of another active command.
If the abovementioned access is made, unnecessary data is outputted. In order to make an access to an adjacent page area from the end of the above page area, it is necessary to issue a new active command to perform active operation on the adjacent page area.
Specifically, in the up mode, when SB=1, 2 and 3, an access is made to the byte data of CA=#FF within the page area where RA=#n and to the byte data of CA=#00 within the page area where RA=#n+1. In the down mode, when SB=0, 1 and 2, an access is made to the byte data of CA=#FF within the page area where RA=#n and to the byte data of CA=#00 within the page area where RA#n+1. In this case, an access needs to be made to adjacent page areas, thus the page area with the row address RA=#n that is provided along with the active command ACT is activated, and, in response to the column address CA=#FF and start byte signal SB=2 that are supplied along with the read command RD, the page area with the adjacent row address RA=#n+1 is activated. Thus, word lines within a plurality of banks are activated in response to one active command ACT.
When control is performed such that the plurality of banks are activated simultaneously, data of required areas can be inputted/outputted economically, even if the byte boundary functions are requested at the end of the page area.
[Other Application of Byte Boundary Functions]
The byte boundary functions can input/output data efficiently when storing the image data to the memory and accessing the data corresponding to an arbitrary pixel. The byte boundary functions have the same benefits in an application other than the image memory.
However, there is a case where the size of data to be processed by the system is less than that of the word configuration of the memory. As a countermeasure for such a case, there is a method padding so that the data of the word configuration size or smaller does not extend across a plurality of column address CA areas. In the example shown in
Suppose that there is a case where data 0 through 5 of the sizes, 2 Byte, 4 Byte, 1 Byte, 2 Byte, 2 Byte and 1 Byte, are continuously stored in the memory, as with the write data 482 shown in the figure. In this case, by performing the write operation as in 481 in the figure, padding is performed in several byte areas within the memory as shown in 483 in the figure, and a total of 4 bytes of areas are not used effectively for storing the data. In this case, the amount of memory is not used effectively. However, by outputting data in a unit of 4 bytes by the column address CA, each data item can be read at one column address access, thus reading speed increases.
However, in order to eliminate the above mentioned redundant storage capacity, the data items may be stored continuously in to the byte areas of the memory without performing padding. For example, the data is written in three cycles by means of a write command WR as shown in 491 in
By writing the data in the manner shown in
Therefore, as shown in 500 in
[Memory Controller for Byte Boundary Functions]
Next, the memory controller for the byte boundary functions is described. The image processing system is described with reference to
An MPEG decoder decodes current image data on the basis of the reference image R-IMG within a past image or future image that is read from the memory on the basis of the motion vector, and on the basis of differential data between the reference image and the current image data. Therefore, an operation is frequently performed in which a rectangular reference image located in the position of the motion vector is read out from the image that is temporarily stored in the image memory 86. In this rectangular access control, the access efficiency can be improved by using the image memory 86 having the byte boundary functions and the memory controller 82 corresponding to the byte boundary functions.
On the other hand, the memory controller 82 computes addresses Add within the memory space (bank address, row address, column address) on the basis of the information items (POSX, POSY), SIZEY and SIZEX specifying the reference image area, and supplies the command CMD, addresses Add, multi-bank access information SA′, start byte signal SB, write data Data and the like to the memory 86. Also, the memory controller 82 receives the read data Data read from the memory 86.
The command CMD issued by the memory controller 82 includes, for example, the mode register set command, active command, read command, write command, precharge command, refresh command, and other commands required in normal SDRAM. Furthermore, in a setting register 543 within the memory controller 82, the address of an upper-left pixel of the frame image FM-IMG, the memory mapping information, and information on the functions provided in the memory 86 are set. The functions provided in the memory are the multi-bank access function, the function of switching around the arrangements of the data corresponding to the endians, and other functions. The presence of the functions provided in the memory, the target of control, is set in the setting register 543.
The reference image specifying information (POSX, POSY), SIZEY, and SIZEX that are computed in the manner described above are outputted from the reference image controller 514 to the memory controller 82, and, on the basis of the reference image specifying information, memory mapping information, and upper-left addresses in the frame area that are set in the setting register 543, the command/address generating sections 542 within the memory controller 82 generates an address of the memory space required in rectangular access.
POSX=0+8+13=21
POSY=0+8+4=12
SIZEX=8,SIZEY=8
The rectangular area of the reference image RIMG does not conform to the unit of a 4-byte area selected by a column address. In order to conform the rectangular area to the unit of the 4-byte area, an access needs to be made to the area with the upper-left coordinate (20 and 12), width 12 and height 8, such as an enlarged area E-RIMG in
In
In response to this access request REQ, the memory controller issues an active command ACT, bank address BA=0, and row address RA=0 to the image memory, and causes the memory to perform active operation. Thereafter, the memory controller issues an read command RD, bank address BA=0, and column address CA=5, 6, 7 through 117, 118, 119 (24 times) in synchronization with a clock CLK, and receives 4-byte data twenty-four times. Then, the memory controller changes the level of a strobe signal STB to H level, and sends the received data to the reading controller.
In this case, the same signal as the one shown in
Also, although not shown, in the memory having the automatic internal column address generating function shown in
As shown in
The memory controller issues a bank address BA=0, row address RA=0, and multi-bank access information SA′=10 (showing an access to two adjacent banks in a lateral direction) along with an active command ACT. In response to this issuance, the image memory performs active operation on the bank BA=0. The memory controller then issues start byte signal SB=01, bank address BA, and column address CA sequentially along with a read command RD. In response to this column address CA=15, the image memory performs active operation on the bank of BA=1. The memory controller receives 16 bytes of data in response to the read command RD issued 16 times. Moreover, the memory controller sends the received 16-byte data to the reference image reading controller.
In this manner, the memory controller may issue the active command once to the memory having the multi-bank access function, even in the case of data across a different bank boundary.
The memory controller computes BA, RA, CA, SB and SA′ to be issued when making the rectangular access, on the basis of these rectangular parameters (POSX, POSY) (SIZEX, SIZEY), and the memory map information and information on the frame image address that are set in the setting register (S4). When the multi-bank active function is ON (YES in S5), the memory controller receives read data while issuing the BA, RA, and SA′ along with an active command ACT and further issuing the BA, CA, and SB along with a read command RD (S6, S7 and S8). In the case of the write operation, the memory controller outputs write data while sequentially issuing the BA, CA and SB along with a write command WR instead of a read command.
Moreover, when the multi-bank active function is OFF (NO in S5), the memory controller checks whether or not the requested rectangle extends across the page area, i.e., bank (S9). If the rectangle does not extend across the bank (NO in S9), the memory controller receive the read data while issuing BA and RA along with the active command ACT and further issuing BA, CA and SB along with the read command RD sequentially (10, 11 and 12). In the case of the write operation, the memory controller outputs write data while sequentially issuing the BA, CA and SB along with a write command WR instead of a read command.
Furthermore, if the rectangle extends across the bank (YES in S9), the byte boundary functions cannot be used, hence the memory controller computes the coordinate POSX and the width SIZEX of the enlarged rectangular area E-RIMG shown in
It should be noted that when the byte boundary functions are set to OFF in the setting register of the memory controller, the memory controller issues the active command, read command, and required addresses by performing the configurations S13 through S18 of
In this manner, the memory controller can set ON and OFF of the byte boundary functions and ON and OFF of the multi-bank active functions into the built-in setting register, and appropriately issues required commands and addresses, as well as the multi-bank information, start byte information, and byte combination information such as the up mode, down mode and alternative, in accordance with the functions of the image memory to be controlled.
Next, the memory controller computes BA, RA, CA, SB and SA′ to be issued when making the rectangular access, on the basis of these rectangular parameters (POSX and POSY) (SIZEX and SIZEY), and the memory map information and information on the frame image address that are set in the setting register (S23). Then, when the output data rearranging function is set to ON (YES in S24), the memory controller issues the bank address BA, row address RA and multi-bank information SA′ along with the active command, and further issues the bank address BA, column address CA, and start byte information SB along with the read command (S25). Thereafter, the memory controller repeatedly issues the read command, BA, CA, and SB until reading of all data items is finished (S26 and S27).
On the other hand, when the output data rearranging function is set to OFF (NO in S24), the memory controller issues the bank address BA, row address RA, and multi-bank information SA′ along with the active command, and further issues the bank address BA, column address CA, and start byte information SB along with the read command (S25). Thereafter, the memory controller repeatedly issues the read command, BA, CA, and SB until reading of all data items is finished, and rearranges the data items so that the received data items are arranged in order of the original image data items (S28, S29 and S30).
It should be noted that the present embodiment explains an example of the image memory that stores digital image data in which image data items of a plurality of pixels are arranged two-dimensionally. However, the present invention can applied to not only the image memory for storing image data, but also a memory device that stores two-dimensionally arranged data, other than image data, on the basis of a predetermined mapping rule. When the stored data items are arranged two-dimensionally, in the case where an arbitrary rectangular area within the two-dimensionally arranged data is accessed, sometimes the data extending across a plurality of memory unit areas needs to be accessed. In this case as well, the present invention can be applied.
<<Multi-Bank Access>>
Next, there is described multi-bank access for preventing the decrease of access efficiency caused when accessing a rectangular area having a plurality of page areas as a problem of the rectangular access. The multi-bank access function involved in rectangular access has been already described with reference to
According to the memory mapping 12, page areas that are adjacent to each other horizontally and vertically are allocated to different banks. Therefore, in order to access the rectangular area 22 shown in
In the present embodiment, therefore, the memory device is set into a mode register that incorporates therein raw address step information RS=4 (a reference numeral 671 in the figure) supplied along with a command, in response to an extended mode register set command EMRS (a reference numeral 670 in the figure), as shown in the timing chart in
Once a rectangular access is generated, the memory device is supplied with a bank address BA=3, row address RA=0 and multi-bank information SA′=4 (a reference numeral 673 in the figure) along with an active command ACT (a reference numeral 672 in the figure). More specifically, once the memory controller detects that the rectangular area to be accessed straddles the four page areas on the memory map, i.e., that the access needs to be made to the four banks, the memory controller supplies the number of access target banks, namely “4”, as the multi-bank information SA′ to the image memory device, in response to a rectangular access request sent from the image processing unit.
In response to this active command ACT and the multi-bank information SA′, the memory device activates, the bank BA3, the bank BA2 adjacent thereto in the row direction, the bank BA1 adjacent to the same in the column direction, and the bank BA0 in the lower right. In this case, the row controller within the image memory generates a bank activation signal for each of the plurality of banks, and further generates a row address as a target of active operation within each bank, on the basis of the bank address BA=3, row address RA=0 and multi-bank information SA′=4 that are supplied along with the active command ACT, as well as the row address step information RS=4 that is stored in the mode register. According to the memory mapping 12 shown in the figure, the four row addresses as the target of active operation are, respectively, RA, RA+1, RA+RS, RA+RS+1, with respect to the supplied row address RA. These four row addresses are supplied to the corresponding four banks in response to the supplied bank address BA. Then, the plurality of banks within the memory device perform active operation on the basis of the bank activation signals and row addresses generated within the image memory.
Therefore, in the example shown in
Then, the memory device repeatedly supplies read commands RD (a reference numeral 674 in the figure) along with the bank address BA and the column address CA, and reads the data item of the corresponding memory unit area specified by a bank address BA and a column address CA, in response to each of the read commands. In the case of a write command, the memory device writes the data item to a memory unit area corresponding to a bank address BA and a column address CA that are supplied along with a write command. In the example shown in
In this manner, according to the multi-bank access function of the present embodiment, the memory device responds to a single active command (first operation command) to perform active operation on the page areas of a plurality of access-target banks beforehand, on the basis of the bank address BA and row address RA to be supplied, the multi-bank information SA′, and the row address step information RS that is set in advance. Therefore, in a subsequent column access, a bank address BA and a column address CA are supplied along with a read command or a write command properly, whereby the rectangular access is performed.
It should be noted in the example shown in
Also, in the example shown in
The operation of the memory device corresponding to the above-described two types of multi-bank information SA′ is described hereinafter with reference to
First of all, the memory device sets step number data RS=4 of the row addresses in the memory mapping to the mode register by means of the extended mode register set command EMRS. Then, in response to the bank address BA3 and row address RA2 for specifying the leading page area, as well as the multi-bank information SA′=4 (a reference numeral 673 in the figure), the bank address BA3, row address RA2 and the multi-bank information SA′ being supplied along with the active command ACT, the memory device generates row addresses RA7, 6 and 3 within the four banks Bank 0 through 3, and performs active operation on the page areas corresponding to the four row addresses including the supplied row address RA2 (a reference numeral 690 in the figure). As a result, the four banks enter an active state and memory access thereto is now possible within the memory device.
Thereafter, addresses BA3/CA127, BA2/CA124, BA1/CA3, BA0/CA0 and the like are supplied along with sixteen read commands RD (a reference numeral 674 in the figure), in response to which the memory device outputs 4 bytes of data from the corresponding banks to the input/output terminals DQ respectively, after a predetermined latency.
Supply of SA′=4 as the multi-bank information SA′ proves that an access is made to a 2×2 page area, so that the memory device can execute active operation on the four banks in response to the active command ACT. Moreover, once the row address RA of the leading bank is supplied, row addresses of the rest of the banks can be calculated on the basis of the row address step information RS.
The row address step number data RS=4 (a reference numeral 671 in the figure) and step number data of the column addresses within the page area, CST=128 (a reference numeral 677 in the figure), are set into the mode register by means of the extended mode register set command EMRS. Further, the bank address BA3 and row address RA2 are supplied along with the active command ACT (a reference numeral 672 in the figure), and the size information 8×8 of the rectangular access area (a reference numeral 676 in the figure) is supplied as the multi-bank information SA′ (a reference numeral 675 in the figure). In response to this active command, the memory device performs active operation on the page area having the supplied addresses BA3 and RA2 (a reference numeral 700 in the figure). The memory device then obtains the rest of the banks Bank 0, 1 and 2 to be accessed, and the row addresses thereof RA 7, 6 and 3 on the basis of the step number data CST=128, the column address CA127 supplied along with the first read command RD, and the rectangle size information 8×8, and performs active operation on the page area of each of these banks (a reference numeral 701 in the figure).
Thereafter, the memory device outputs 4 bytes of data from each of the corresponding banks to the input/output terminals DQ (a reference numeral 702 in the figure) in response to the sixteen read commands (a reference numeral 674 in the figure).
In this manner, when the rectangle size is supplied as the multi-bank information SA′, the memory device determines whether access is made across a plurality of banks, on the basis of the supplied column addresses and memory mapping (column address step number CST), generates an activation signal for each bank that is a target of active operation, as well as a row address of each bank, and performs active operation sequentially. Therefore, activation operation is performed on the banks Bank 0, 1 and 2 after the leading column address CA=127 is supplied.
A command controller 95 decodes a command that is supplied from a combination of signals RAS, CAS, WE and CS specifying commands. The row address step number data RS of the memory mapping is supplied along with the extended mode register set command EMRS from address terminals Add, and the row address step number data RS are set into a mode register 96. In this case, the type of data that is set is specified by a bank address BA, and the step number data RS is set into a register area corresponding to this bank address BA.
The command controller 95 generates an active pulse actpz instructing for start of operation on the row side, in response to the active command ACT. The multi-bank activation controller 88 distributes this active pulse actpz to the banks to be activated, which are determined from the supplied bank address BA and the multi-bank number data SA′. This pulse signal to be distributes is the bank activation signals actpz 0 through 3. The multi-bank information SA′ is inputted from the special terminals SP0 and SP1 when the active command ACT is issued. Also, the row addresses RA are inputted from the address terminals Add.
Moreover, the row address calculator 97 generates four row addresses RA, RA+1, RA+RS, and RA+RS+1 on the basis of the bank address BA and row address RA to be supplied, the step number data RS set in the mode register 96, and the memory mapping. Then, these four row addresses are supplied to a group of 2×2 banks having a bank with the supplied bank address BA on the upper left portion.
Each of the banks has a memory core having a memory array MA and a decoder Dec, and a core controller (not shown) that controls the memory core. The core controller performs activation control to the memory core within each bank in response to the bank activation signals actpz 0 through 3 described above. In this case, the abovementioned bank address BA is supplied to each row decoder, the corresponding word lines are driven, and then a group of sense amplifiers are activated. This is the activation operation (active operation) performed in the banks.
Hereinafter, operation of selecting banks to be activated within the memory device, control of the timing of bank activation, row address generating operation, and bank allocation setting operation in the memory mapping are specifically described as the functions required in the multi-bank access.
[Selecting Banks]
The timing chart is same as the abovementioned example, wherein, along with the extended mode register set command EMRS, a register setting data V and the step number data RS are inputted to a bank address terminal BA and an address terminal ADD respectively, and then set into the mode register. Furthermore, a bank address BA, a row address RA, and the multi-bank information SA′ are inputted along with the active command ACT.
The memory device latches the multi-bank information items SA′ 0, 1 and bank addresses BA 0, 1 that are inputted to each input buffer 94 to a latch circuit 720 in synchronization with a clock CLK. The multi-bank activation controller 88 has a bank decoder 88A that decodes the bank addresses BA 0 and 1 to generate four bank selection signals bnkz<3:0>, and a bank active pulse output circuit 88B that generates bank activation signals actpz<3:0> allocated with the active pulses actpz, in response to the bank selection signals.
In the case of SA′=01, there are two banks to be activated in the horizontal direction, thus the bank decoder 88A degenerates (ignores) the bank address BA0 and brings the bank selection signal bnkz<3:0> of two banks selected only by the bank address BA1 to H level. Along with this operation, there is generated a bank activation signal actpz<3:0> of the bank selected by the supplied bank address and the adjacent bank, in the row direction.
In the case of SA′=10, there are two banks to be activated in the horizontal direction, thus the bank decoder 88A degenerates (ignores) the bank address BA1 and brings the bank selection signal bnkz<3:0> of two banks selected only by the bank address BA0 to H level. Along with this operation, there is generated a bank activation signal actpz<3:0> of the bank selected by the supplied bank address and the adjacent band, in the column direction.
In the case of SA′=11, there are a total of four banks to be activated in the horizontal and vertical directions, thus the bank decoder 88A degenerates (ignores) the bank addresses BA0 and BA1 and brings the bank selection signals bnkz<3:0> of all four banks to H level. Along with this operation, there are generated bank activation signals actpz<3:0> of four banks adjacent to, in the row and column directions, the banks selected by the supplied bank address.
Degeneration of the bank addresses performed by the bank decoder is a control of bringing the corresponding bank addresses BA and inversion signals/BA thereof to H level. Accordingly, the bank decoder 88A ignores these bank addresses and selects a bank by means of the remaining bank addresses.
Returning to
According to the second example described above, the upper left leading bank is selected by the supplied bank address, and the right, lower, and lower right banks are accordingly selected by 3 bits of simultaneously activated-bank data items SA′ 0 through 2. Therefore, two banks in an oblique direction can be simultaneously activated, or three banks can be simultaneously activated, and a combination of banks to be simultaneously activated can be changed flexibly. Therefore, the second example can be accommodated to an access made to special areas.
As shown in the timing chart of
The activating bank determination circuit 88D of the multi-bank activation controller 88 determines bank to be simultaneously activated, on the basis of the step number data CST, the rectangle size information W, H and the column address CA. This determination algorithm is shown in
As shown in the activating bank determination algorithm of
To explain the example shown in
The activating bank determination circuit 88D uses the above-described determination algorithm to determine banks to be simultaneously activated. As a result, the activating bank determination circuit 88D outputs a bank address degenerate signal 88E to the bank decoder 88A. Specifically, in the case in which the banks in the horizontal direction are straddled, the bank address BA0 is degenerated, and in the case in which the banks in the vertical direction are straddled, the bank address BA1 is degenerated. This degenerate signal 88E is the same as the multi-bank information SA′0, 1 shown in
More specifically, in the third example, the activating bank determination function that the memory controller performs in the first and second examples is provided in the memory device. If the activating bank determination algorithm described above is provided within the memory controller, the multi-bank information SA′0, 1 shown in
As described above, in order to realize the multi-bank activation function, the multi-bank activation controller 88 generates the bank selection signal bnkz<3:0> of a bank to be activated, on the basis of the input data, further generates the bank activation signal actpz<3:0> on the basis of the generated bank selection signal bnkz<3:0>, and controls the activation operation of the banks to be activated.
[Bank Activation Timing]
The multi-bank activation controller 88 supplies the bank activation signal actpz<3:0> to banks to be activated, and each of the banks starts the activation operation on a page area in response to this bank activation signal. In this case, it is preferred to control the timing for activating a plurality of banks. For example, a control for performing the activation control on the plurality of banks simultaneously, and a control for performing the activation operation on the plurality of banks at different times can be considered. In the former case, there are no restrictions on timings for inputting a subsequent read command or write command. In the latter case, on the other hand, the plurality of banks do not perform the activation operation simultaneously, thus an instantaneous increase of consumed current can be avoided.
Each of banks bank 0 through 3 has a memory core 781 including a memory cell array, and a core control circuit 780 for controlling the memory core. In response to the bank activation signals actpz<3:0>, each core control circuit 780 activates a row decoder within the memory core 780, drives the word lines corresponding to the row addresses, and activates a row of sense amplifiers.
In Example 1 shown in
The multi-bank activation controller 88 is constituted by an activating bank control circuit 88C and the bank active pulse output circuit 88B. The activating bank control circuit 88C has incorporated therein the function of the bank decoder described above, determines an order of performing activation on banks to be activated, on the basis of the supplied bank address BA[1:0] and the multi-bank data SA′[1:0], and supplies a selection signal 795 to the selectors SEL. This selection signal 795 consists of 8 bits. Two bits of the selection signal are supplied to each selector, and each selector outputs the bank activation signal actpz<3:0> to the banks to be activated, in response to the selection signal 795.
It should be noted that the delay circuits 791 through 793 generate the necessary delay active pulses actpz 1 through 3 in accordance with the activated-bank number data 790, and thereby enables power saving.
In the case in which the multi-bank data SA′[1:0]=11, all of the four banks are activated, and the activation order (00, 01, 10, 11) differs according to the supplied bank addresses BA[1:0], as shown in the activation order data table 800. For example, in the case in which the supplied bank address BA[1:0]=00, activation control is performed in order of the banks Bank 0, 1, 2 and 3. The activation order data (8 bits of 00, 01, 10, 11) shown in the table 800 corresponds to the 8-bit selection signal 795 that is generated by the activation bank control circuit 88C shown in
Furthermore, in the case in which the supplied bank address BA[1:0]=01, the activation control is performed in order of the banks Bank 1, 0, 3 and 2. The bank activation signals actpz <0> through <3> in this case are shown in the timing chart of
Similarly, in the case in which the multi-bank data SA′[1:0]=01, two banks in the horizontal direction are activated, and, as shown in the activation order data table 801, two activation order data items (00, 01) are generated in response to the supplied bank addresses BA[1:0].
Similarly, in the case in which the multi-bank data SA′ [1:0]=10, two banks in the vertical direction are activated, and, as shown in the activation order data table 802, two activation order data items (00, 10) are generated in response to the supplied bank addresses BA[1:0]. According to this table 802, in order to activate the two banks, the active pulse actpz 0 and the delay active pulse actpz 2 are used to generate a bank activation signal, since the table 802 and thetable 800 are in common. Specifically, as shown in a timing chart 803 below the table 802, the internal active command ACT is generated at the timing of the active pulse actpz 0 and of the delay active pulse actpz 2 in response to a supplied active command ACT.
Therefore, in the case in which the multi-bank data SA′ [1:0]=10, the activation order data (00, 01) shown in a table 804 may be generated, in place of the one shown in the table 802. In this case, as shown in a timing chart 805 below the table 804, the internal active command ACT is generated at the timing of the active pulse actpz 0 and of the delay active pulse actpz 1 in response to the supplied active command ACT. Specifically, the two banks to be activated simultaneously are activated successively at different timings.
According to this Example 3, since the delay circuits are the flip-flop circuits 810 through 312 synchronized with the clock CLK, three delay active pulses actpz 1 through 3 are generated from the active pulse actpz 0 at the delay timing synchronized with the clock CLK. Specifically, as shown in the timing chart of
[Generating Row Address]
The multi-bank access function of the present embodiment performs activation control on all page areas of the banks required to be accessed, in response to the active command ACT inputted once, a bank address, and a row address. Therefore, on the basis of the supplied bank address and row address, the banks required to be activated need to be determined, and row addresses need to be generated for specifying page areas required to be activated.
This figure shows the memory mapping 12, a logical value table 820 showing supplied bank addresses BA 0, 1 corresponding to rectangular access areas RC 0 through 3, as well as a row address RA as a target of activating each bank. The memory mapping 12 is the same as the one described above, wherein, in the page areas arranged in the row and column directions, the banks of the page areas adjacent to each other vertically and horizontally are different from each other, and the row address is incremented by one for every four banks Bank 0 through 3 adjacent to one another vertically and horizontally.
According to this memory mapping 12, in the case of a rectangular area RC0 to be accessed, it is evident from the supplied bank address BA=BA0 (=00) and the supplied row address RA=RA0 that the addresses of page areas to be activated simultaneously are BA0/RA0, BA1/RA0, BA2/RA0, BA3/RA0. In the case of a rectangular area RC1, it is evident from the supplied bank address BA=BA1 (=01) and row address RA=RA0 that the addresses of page areas to be activated simultaneously are BA1/RA0, BA0/RA1, BA3/RA0, BA2/RA1. In the case of a rectangular area RC2, it is evident from the supplied bank address BA=BA2 (=10) and row address RA=RA0 that the addresses of page areas to be activated simultaneously are BA2/RA0, BA3/RA0, BA0/RA(0+RS), BA2/RA(0+RS). In the case of a rectangular area RC3, it is evident from the supplied bank address BA=BA3 (=11) and row address RA=RA0 that the addresses of page areas to be activated simultaneously are BA3/RA0, BA2/RA(0+1), BA1/RA(0+RS), BA2/RA(0+RS+1).
To generalize the above addresses, in the case in which the supplied row address is RA and the step number of the row address of the memory mapping 12 is RS, a row address to be generated in each of the banks Bank 0 through 3 is as shown in the logical value table 820 in response to the supplied bank addresses BA0, BA1. Specifically, the row addresses to be generated are as follows:
BA=00:RA, RA, RA, RA BA=01:RA+1, RA, RA+1, RA BA=10:RA+RS, RA+RS, RA, RA BA=11:RA+RS+1, RA+RS, RA+1, RATherefore, the row address calculator 97 shown in
For example, in the case in which the supplied bank address BA=01, the row address control circuit 832 generates “01, 00, 01, 00” as the selection signal 835, in response to which each of the selectors SEL selects RA+1, RA, RA+1, RA, beginning at the top, and supplies the selected row addresses to the address decoders 836 of the banks respectively. In the banks, the address decoders 836 of selected banks are activated in response to the abovementioned bank activation signal actpz<3:0>, the activated address decoders then decode the above-described row addresses RA+1, RA, RA+1, RA, and corresponding word lines are activated.
As described above, the row address calculator 97 generates four necessary row addresses from the row addresses RA to be supplied. Therefore, the memory device can internally generate the four necessary row addresses by inputting the row addresses by means of single active command, whereby a plurality of banks can be activated.
[Memory Mapping Setting]
In order to realize the multi-bank activation function, it is necessary to set the memory mapping information in the memory device. For example, as described with reference to
As shown in the timing chart of
In response to the memory mapping information AR set into the mode register 96, the selectors SEL of the bank address switching circuit 861 selects either 2-bit bank address BA0 or BA1 to generate an internal bank addresses ba0Z and ba1z respectively. As shown in the figure, in the case where memory mapping information AR=L, the internal bank addresses are set into ba0z=BA0 and ba1z=BA1, and in the case where memory mapping information AR=H, the internal bank addresses are set into ba0z=BA1 and ba1z=BA0.
In this manner, by switching the bank addresses BA0, BA1 by means of the input section on the basis of the memory mapping information AR, the bank selection function and row address generation function incorporated in the memory device can be configured based on the common memory mapping 12A.
It should be noted in the above embodiment that although the multi-bank information (SA′), the simultaneously activated bank data (SA′ 0 through 2), the rectangular area size data (W, H) and the like are inputted from the special input terminal SP, such input can be realized by unused terminals. For example, in a read operation, if row addresses are inputted by the address terminals Add 0 through 12 and column addresses are inputted by the address terminals Add 0 through 9, the address terminals Add 10 through 12 are not used when the column addresses are inputted. Therefore, these control data items SA′, W, H and the like can be inputted from these unused address terminals Add 10 through 12 when inputting the column addresses. The present invention can be applied to such a case.
Moreover, various information items that are set into the mode register by the extended mode register set command EMRS are not limited to the descriptions of the above embodiment, thus the applicable scope of the present invention comprises inputting these various information items from the address terminals.
<<Multi-bank Access and Byte Boundary>>
There has been described that the memory device has the byte boundary function in order to respond to a rectangular access that across the boundary of memory unit area selected by bank address and column address. There has also been described that the memory device has the multi-bank access function in order to respond to the case where a rectangular access is made across the boundary of page area selected by bank addresses and row addresses. Here, in the case in which a rectangular access area acrosses the boundary of page areas as well as memory unit areas, the both functions can allow access to be made by a single input of an active command and can eliminate unnecessary data outputs. Specific examples of this case are described hereinafter.
As the row controllers, there are provided the multi-bank activation controller 88 that generates, from a bank address BA and multi-bank information SA′, bank activation signals actpz<3:0> of banks to be activated, and row address calculators 97-2, 97-3 that calculate a row address of each bank from a bank address BA, row address RA, and step number data RS of the row address. These row address calculators 97-2, 97-3 are each a part of the configurations described with reference to
The column controller 90 has column address controllers 290-2, 290-3 that generate internal column addresses I-CA-2, 3 in each bank from a column address CA and bank address BA to be supplied, as well as from the start byte signal SB and the step number data CST of the column address. These column address controllers 290 are the same as the column address generating section shown in
Moreover, the column controller 90 generates a control signal S221 for selecting data of byte areas Byte 0 through 3 within each bank, on the basis of the bank address BA and column address CA to be supplied, as well as the start byte signal SB. The data latch circuits within these four byte areas Byte 0 through 3 within each bank are selected by the control signal S221, and the selected data latch circuits are connected to an input/output I/O bus. The configurations and operations of the byte areas Bytes 0 through 3 within each bank are the same as those described with reference to
The operation that is performed when the rectangular area 22 shown in
Next, bank addresses BA and row addresses RA of page areas with pixels in the upper left portion of the rectangular access, as well as multi-bank information SA′=4 (a reference numeral 873 in the figure), are inputted along with an active command ACT (a reference numeral 876 in the figure). When SA′=4, simultaneous activation of 2×2=4 banks. In response to this, the multi-bank activation controller 88 outputs the bank activation signals actpz<3:0> to these four banks. Furthermore, the row address calculators 97-2, 3 calculate a row address of each of the banks. Then, row decoders of the four banks decode the calculated row address to drive the corresponding word lines, and then the banks are activated.
Thereafter, a bank address BA=3, a column address CA 126, a start byte signal SB=2 (a reference numeral 874 in the figure), and second information of the byte combination information BMR=UP (a reference numeral 875 in the figure) are inputted along with a read command RD (a reference numeral 877 in the figure). The column address controller 290-3 of Bank 3 corresponding to this bank address BA generates a column address CA=126, 127 on the basis of the supplied column address CA=126 and the start byte signal SB=2, and outputs the column address CA=127 as the internal column address I-CA-3. Accordingly, Bank 3 causes each of the byte areas Bytes 0 through 3 to output data on the column addresses 126, 127. Then, in response to the control signal S221 inputted from a data latch selector 221, the byte areas Bytes 2, 3 and the byte areas Bytes 0, 1 output the data on the column address CA=126 and the data on the column address CA=127 to the I/O bus, respectively.
Next, the bank address BA=3, column address CA=127, SB=2, and BMR=UP are inputted along with the read command RD. In response to this, the column address controller 290-3 generates the internal column address I-CA-3=127, and Bank 3 outputs 4-byte data of the column address 127. On the other hand, the column address controller 290-2 detects, from the bank address BA=3, column address CA=127, and start byte signal SB=2, that the data needs to be read from Bank 2, and refers to the step number data CST of the column address to output a column address CA=124 of Bank 2 as the internal column address I-CA-2. Consequently, Bank 2 reads 4-byte data of the column address CA=124. Then, the data latch selector 221 generates the control signal S221 on the basis of the bank address BA=3, column address CA=127, and start byte signal SB=2, and the data on the byte areas Bytes 2, 3 and the data on the byte areas Bytes 0, 1 are outputted from Bank 3 and Bank 2, respectively, to the I/O bus.
Subsequently, column addresses CA=2, 3, 6, 7, corresponding to the bank address BA=1 are inputted along with the read command RD, the column address controllers 290 similarly generate required column addresses, the data latch selector 221 generate the required control signal S221, and 4-byte data of the position corresponding to the start byte signal SB=2 is outputted from the same bank or an adjacent bank.
Although the above description was about the operation of the read command, the same column access control is performed in the case of a write command as well.
According to the present embodiment, with respect to the rectangular access that is made across page areas and straddles a plurality of banks, access can be made from arbitrary bytes (orbits) within a memory unit area to 4-byte data (or 4-bit data), on the basis of the start byte signal SB and the byte combination information BMR.
[Memory Controller Responding to Multi-Bank Access]
The memory controller for controlling the memory device having the multi-bank access function is described next. As described with reference to
In this memory mapping 12, eight page areas are arranged in the horizontal direction, and four page areas are arranged in the vertical direction. Therefore, in this memory mapping 12 the number of pixels in the horizontal direction is 128 (=16 pixels×eight page areas), and the number of pixels in the vertical direction is also 128 (=32 rows×four page areas). Various computation processes are described hereinafter based on this memory mapping.
Therefore, the interfaces IF_1 through IF_n exchange data with the access request source blocks 81. There are two types of accesses made from the access source blocks: horizontal access and rectangular access. The arbitration circuit 540 arbitrates the access requests sent from the interfaces, and outputs an access instruction to the sequencer SEQ_n that has acquired the access right. The selector SEL then selects a command and address from the sequencers SEQ_1 through SEQ_n in response to a selections signal S540 sent from the arbitration circuit 540, and outputs the selected command and address to the memory device 86. The selector SEL further selects a data line Data from the interfaces IF_1 through IF_n in response to the selection signal S540.
In a register 543 various parameters are set from the host CPU. The parameters include function data on whether the memory device 86 has the byte boundary function and the multi-bank access function. In addition, configuration parameters include a row address of an upper left pixel on the frame image ROW_BASE_ADR, the number of pixels in the horizontal direction of the frame image PICTURE_MAX_XSIZE, and the like.
The memory device 86 is an image memory having the abovementioned byte boundary function and multi-bank access function. The memory controller 82 and the memory device 86 shown in
It should be noted that the frame image FM-IMG corresponds to the memory mapping 12 in
On the other hand, in the rectangular access (at the time of writing) shown in
In the case of the horizontal access as well, the access source blocks supply the leading address ADR of the horizontal access and horizontal access size SIZE, receive the read data RDATA in the case of reading, and output the write data RDATA in the case of writing. Specifically, as shown in
The sequencer SEQ_n issues a command on the basis of the abovementioned parameters and the parameters set in the register, and begins accessing the memory device 86. In accordance with the status of issuance of the command, the sequencer SEQ_n issues the enable signal EN corresponding to the amount of data, and this enable signal EN is transmitted to the access request source 81—n via the interface IF_n. In the case in which reading is performed, the read data is transmitted from the memory device 86 to the access request source 81—n via the interface IF_n in response to the enable signal EN described above. In the case in which writing is performed, the write data is transferred from the access request source 81—n to the memory device 86 via the interface IF_n in response to the enable signal EN described above.
In this manner, during the access control process in which the command is issued to the memory device 86, the sequencer SEQ_n asserts, to the arbitration circuit 540, an active signal ACTIVE indicating that the data is being accessed. Once the access to the memory is ended, the active signal ACTIVE is negated.
PICTURE_MAX XSIZE=128
ROW_BASE_ADR=0
(X_POS, Y_POS)=(28, 94)
(X_SIZE, Y_SIZE)=(8, 4)
Moreover,
The intermediate parameter generating section 941 generates the intermediate parameter by means of the following computation.
(1) In the case in which the rectangular data RIMG straddles the four page areas, the upper left bank address BA can be obtained in the manner described next. In the following manner, first of all, the frame pixel coordinates (X_POS, Y_POS) of the upper left pixel of the rectangular data RIMG within the frame image FM-IMG are obtained, and these coordinates are divided by the number of horizontal pixels 16 and the number of vertical pixels 32 of the page area respectively, whereby a bank X address BA_X_ADR and a bank Y address BA_Y_ADR are obtained. Each remainder obtained in this division is rounded.
BA_X_ADR=X_POS/16
BA_Y_ADR=Y_POS/32
The bank X address BA_X_ADR and the bank Y address BA_Y_ADR each indicates which page area in the horizontal direction or vertical direction in the memory mapping 12 the upper left pixel of the rectangular area corresponds. It should be noted that the upper left portion of the memory mapping 12 is located at the 0th page area in the horizontal direction and the 0th page area in the vertical direction.
The following bank addresses BA[1:0] are obtained depending on whether the obtained bank X address BA_X_ADR and the bank Y address BA_Y_ADR are odd or even.
If the BA_X_ADR is an even number and the BA_Y_ADR is an even number, upper left BA=0
If the BA_X ADR is an odd number and the BA_Y ADR is an even number, upper left BA=1
If the BA_X_ADR is an even number and the BA_Y_ADR is an odd number, upper left BA=2
If the BA_X_ADR is an odd number and the BA_Y_ADR is an odd number, upper left BA=3
(2) The bank address BA on the right side, the bank address BA on the lower side, and the bank address BA on the lower right bank address BA are obtained as follows. Specifically, according to the memory mapping 12, the right BA, lower BA, and lower right BA are obtained, as shown below, from the upper left BA[1:0] obtained in (1) described above. It should be noted that “˜” means an inverted bank address.
Right BA=[upper left BA [1], ˜upper left BA [0]]
Lower BA=[˜upper left BA [1], upper left BA [0]]
Lower right BA=[˜upper left BA [1], ˜upper left BA [0]]
According to the examples shown in
BA_X_ADR=X_POS/16=28/16=1
BA_Y_ADR=Y_POS/32=94/32=2
are established. Also, since BA_X_ADR=1 is odd and BA_Y_ADR=2 is even, the upper left bank address BA[1:0]=01 is established. That is, BA1 can be obtained.
Moreover,
The right BA, lower BA, lower right BA, BA0, BA3, BA2, can be obtained from the upper left BA=2′b01, as follows.
Right BA=[upper left BA [1], ˜upper left BA [0]]=[00]=0
Lower BA=[˜upper left BA [1], upper left BA [0]]=[11]=3
Lower right BA=[˜upper left BA [1], ˜upper left BA [0]]=[10]=2
(3) An access start row address ROW_ADR within the logical address space S86 of the memory is as follows.
ROW_ADR=ROW_BASE_ADR+[PICTURE_MAX_XSIZE/(16* 2)]*[Y_POS/(32*2)]+X_POS/(16*2)
Specifically, ROW_BASE_ADR is a row address of an upper left pixel of the frame image, PICTURE_MAX_XSIZE/(16*2) is the number of row address steps in the horizontal direction within the frame, Y_POS/(32*2) indicates at what number in the vertical direction within the frame the upper left pixel of the rectangular area RIMG is positioned (a reference numeral 961 in
According to the examples shown in
(4) An access start column address COL_ADR in the logical address space S86 of the memory is a column address within a page, and is obtained as follows:
COL_ADR=4*Y_POS %32+(X_POS/4)%4
Here [%] is a remainder. Specifically, the number of steps of the column address within the page area is 4, the number of columns in the horizontal direction in the page area is 4, and the number of rows in the vertical direction is 32, as shown in
According to the examples shown in
(5) Next, since the number of pixels in the horizontal direction of a page area is 16 and the number of pixels within the vertical axis of a page area is 32, the X coordinate (BA_X_POS) and Y coordinate (BA_Y_POS) within the bank are obtained as follows:
BA_X P0S=X_POS %16
BA_Y_POS=Y_POS %32
The results correspond to the coordinates (BA_X_POS, BA_Y_POS) of the upper right pixel of the rectangular area RIMG within the upper right bank (BA1/RA4) shown in
(6) X-direction BANK straddling flag and Y-direction BANK straddling flag indicating whether the rectangular area RIMG straddles a bank (page area) are obtained as follows from the X and Y coordinates within the bank, i.e., BA_X_POS, BA_Y_POS, which are obtained in (5), and the sizes of the rectangular area RIMG in the horizontal direction and vertical direction, i.e., X/Y_SIZE:
If BA_X_POS+X_SIZE>15, X-direction BANK straddling flag=1
If BA_Y_POS+Y_SIZE>31, Y-direction BANK straddling flag=1
Specifically, as shown in
To describe the above (5) and (6) by means of the examples shown in
BA_X_POS=X_POS %16=28%16=12
BA_Y_POS=Y_POS %32=94%32=30
X-direction BANK straddling flag and the Y-direction BANK straddling flag are as follows:
BA_X_POS+X_SIZE=12+8=20, which is higher than 15, thus X-direction BANK straddling flag=1, and
BA_Y_POS+Y_SIZE=30+4=34, which is higher than 31, thus Y-direction BANK straddling flag=1,
thus the bank is straddled by RIMG in both X and Y directions.
(7) Next, the sizes in X, Y directions of a rectangular area straddling four banks, i.e., 1ST_X_SIZE, 2ND_X_SIZE, 1ST_Y_SIZE, 2ND_Y_SIZE, are computed as follows:
As shown in
If X-direction BANK straddling flag=1,
1ST_X_SIZE=16_BA_X_POS
2ND_X_SIZE=X_SIZE—1ST_X_SIZE
If X-direction BANK straddling flag=0,
1ST_X_SIZE=X_SIZE
If Y-direction BANK straddling flag=1,
1ST_Y_SIZE=32−BA_Y_POS
2ND_Y_SIZE=Y_SIZE−1ST_Y_SIZE
If Y-direction BANK straddling flag=0,
1ST_Y_SIZE=Y_SIZE
When the examples shown in
1ST_X_SIZE=16-BA_X_POS=16−12=4
2ND_X_SIZE=X_SIZE−1ST_X_SIZE=8−4=4 and since Y-direction BANK straddling flag=1,
1ST_Y_SIZE=32−BA_Y_POS=32−30=2
2ND_Y_SIZE=Y_XIZE−1ST_Y_SIZE=4−2=2
(8) Finally, the row address step information RS is the number indicating how many row addresses increase when scanning the frame image 12 (FM-IMG) from the left end to the right end in the horizontal direction, and is obtained by the following equation:
RS=PICTURE_MAX—XSIZE/(16*2)
In the examples shown in
RS=PICTURE_MAX—XSIZE/(16*2)=128/32=4
As described above, the intermediate parameter generating section 94 computes the intermediate parameters (1) through (8) by means of the above equations, and outputs the results to the command/address generating section 942. Then, the command/address generating section 942 generates a command, bank address BA, row address RA, column address CA, row address step information RS and multi-bank information SA′ to be supplied to the memory 86, on the basis of the intermediate parameters.
Since whether the memory device to be controlled has the multi-bank access function or not is set in the register 543, this matter is checked (S43). If the multi-bank access function is not set, the normal control operation is performed to repeatedly issue the active command ACT and read command RD (or write command) in accordance with the number of banks (S44).
In the case in which the multi-bank access function is set, the command/address generating section 942 determines the number of banks on the basis of a bank straddling flag Flag [X:Y] (S46). As a result, the command/address generating section 942 generates the multi-bank information SA′ [1:0] from the bank straddling flag Flag [X:Y]. The relationship therebetween is as follows:
Flag [X:Y]=00 SA′[1:0]=00 (one bank is activated)
Flag [X:Y]=10 SA′[1:0]=01 (two banks are activated in the X direction)
Flag [X:Y]=01 SA′ [1:0]=10 (two banks are activated in the Y direction)
Flag [X:Y]=11 SA′ [1:0]=11 (four banks are activated)
Therefore, the command/address generating section 942 issues the multi-bank information SA′ along with the active command ACT, leading bank address BA, and leading row address RA (S80, S70, S60, S50).
In the case in which the four banks are activated simultaneously, the command/address generating section 942 within the memory controller issues the multi-bank information SA′=11 along with the active command ACT and row address RA (S50). Then, the command/address generating section 942 issues a read command or write command along with the column address CA within the upper left bank (S51). This read or write command is repeatedly issued while incrementing the column address a number of times, i.e., 1ST_X_SIZE=N times, corresponding to the access size in the X direction within the upper left bank. Moreover, a read command or write command is issued along with the column address CA within the right bank (S52). This read or write command is repeatedly issued while incrementing the column address a number of times, i.e., 2ND_X_SIZE=N times, corresponding to the access size in the X direction within the upper left bank. Then, the number of lines is incremented by one (S53), and the steps S51, S52 and S53 are repeated until the number of lines exceeds the 1ST_Y_SIZE, which is the access size in the Y direction within the upper left bank (S54).
Next, the command/address generating section 942 issues a read command or write command along with the column address CA of the lower bank (S55). This read or write command is repeatedly issued while incrementing the column address a number of times, i.e., 1ST_X_SIZE=N times, corresponding to the access size in the X direction within the lower bank. Furthermore, a read command or write command is issued along with the column address CA of the lower right bank (S56). This read or write command is repeatedly issued while incrementing the column address a number of times, i.e., 2ND_X_SIZE=N times, corresponding to the access size in the X direction of the right bank. Then the number of lines is incremented by one(S57), and the steps S55, S56 and S58 are repeated until the number of lines exceeds the 2ND_Y_SIZE, which is the access size in the Y direction within the lower bank (S58).
The command/address generating section 942 obtains the column address to be issued along with the abovementioned read or write command, from the leading column address COL_ADR=123 and the column address step number data CST=4, which are the intermediate parameters, on the basis of the memory map.
In the case in which two banks are activated simultaneously in the X direction, the command/address generating section 942 within the memory controller issues the multi-bank information SA′=01 along with the active command ACT and row address RA (S60). Then, a read or write command and a column address are issued N times to the upper left bank (S61), and a read or write command and a column address are issued N times to the right bank (S62). These steps S61, S62 and S63 are repeated until the number of lines exceeds the 1ST_Y_SIZE (S64).
In the case in which two banks are activated simultaneously in the Y direction, the command/address generating section 942 within the memory controller issues the multi-bank information SA′=10 along with the active command ACT and row address RA (S70). Then, a read or write command and a column address are issued N times to the upper left bank (S71), and these steps S71 and S72 are repeated until the number of lines exceeds the 1ST_Y_SIZE (S73). Similarly, a read or write command and a column address are issued to the lower bank (S74, S75, S76).
Finally, in the case in which only one bank is activated, the command/address generating section 942 within the memory controller issues the active command ACT, row address RA, and multi-bank information SA′=00 (S80). Then, a read or write command and a column address are issued N times to the upper left bank (S81), and these steps S81 and S82 are repeated until the number of lines exceeds 1ST_Y_SIZE (S83).
As described above, once the access request REQ and access target area data X/Y_POS, X/Y_SIZE are received from the access source block, the memory controller 82 generates the intermediate parameter from the row address of the frame area ROW_BASE_ADR and the number of pixels in the horizontal direction PICTURE_MAX_XSIZE that are set in the register 543, then determines the number of banks to be activated simultaneously, issues the multi-bank information SA′ corresponding to the result of determination, and then activates the bank within the memory device simultaneously. Accordingly, a plurality of banks can be activated by issuing the active command once, whereby memory access can be performed efficiently.
In the example shown in
Furthermore, the memory controller repeatedly issues a read command RD, a bank address BA and a column address CA. As shown in
In the case in which a plurality of banks are activated by a single active command by means of the multi-bank access function, when the byte boundary function is used to access image data in the middle of a 4-byte area, the memory controller issues a read or write command, a bank address BA, a column address CA, start byte information SB, and memory map information BMR, as shown in
It should be noted that the above embodiment has described an example of an image memory that stores the digital image data in which image data items of a plurality of pixels are arranged two-dimensionally. However, the present invention can be applied to not only the image memory for storing the image data, but also a memory device that can also store two-dimensionally arrayed data items besides the image on the basis of predetermined mapping rules. If the stored data items are arranged two-dimensionally, sometimes the data items of a plurality of page areas need to be accessed when accessing any rectangular area within the two-dimensionally arrayed data. The present invention can be applied in such a case as well.
<<Background Refresh>>
The overview of the background refresh has been described with reference to
As shown in
The background refresh is performed only in a partial area within the memory device (first area). Therefore, in the case of an area other than the refresh target area, the normal memory operation can be performed in parallel with the background refresh. Then, the control circuit 996 executes normal memory operation 998 corresponding to the second operation code 994, in the selected second area 992 in response to the second operation code sent from the memory controller. The second operation code 994 is, for example, an active command, read/write command, or the like. Specifically, the control circuit 996 causes the second area 992 to execute the normal memory operation 998 in response to the second operation code 994 even prior to the completion of the refresh operation 997 executed by the first area 991. The control circuit 996 also causes the first area 991 to execute the refresh operation 997 in response to the first operation code 993 even prior to the completion of the normal memory operation 998 executed by the second area 992.
In this manner, in the background refresh of the present embodiment, the refresh operation in the first area and the normal memory operation in the second area can be executed without waiting for the completion of the other operation. Accordingly, it can be prevented that by executing the refresh operations in all areas within the memory device, the normal memory operations are interrupted during the refresh operation period, and of the effective access efficiency is decreased.
According to the memory refresh specification, the period of time in which all memory areas need to be refreshed, and the number of times that the refresh operation is performed are defined. For example, in a 64 M-bit memory, “64 ms/4096 cycles” is defined. In this case, in order to refresh all of the 64 Mbits of cells within 64 ms, the refresh operation is performed at a frequency of every 15, 6 μs (=64 ms/4096), wherein 16 Kbits (=64M/4096) of cells are refreshed in one refresh operation.
On the other hand, in the case in which the memory cell area 990 is constituted by the first and second areas 991 and 992 as shown in
For example, if a refresh event occurs, the memory controller generates a first operation code and first area information (1010), and issues the first operation code (1013) even if an operation on the second area is not completed (NO in 1011) if the first area and the second area are different (No in 1012). If the first area as a refresh event target is the same as the second area which is being operated (Yes in 1012), the processing is kept in standby until the operation of the second area is completed (Yes in 1011).
Similarly, once the memory operation event occurs, the memory controller generates a second operation code and second area information (1014), and issues the second operation code (1017) as with the above manner even if an operation on the first area is not completed (NO in 1015) if the second area and the first area are different (No in 1016). If the second area as a memory operation event target is the same as the first area which is being operated (Yes in 1016), the processing is kept in standby until the operation on the first area is completed (Yes in 1015).
Therefore, in the horizontal access 1020, the background refresh command BREN (a reference numeral 60 in the figure) is inputted along with the refresh bank information SA (a reference numeral 61 in the figure) indicating the refresh target bank. In this example, the horizontal access 1020 is generated with respect to the banks BA0, BA1, thus the refresh target banks are BA2 and BA3. In response to the background refresh command BREN, the control circuit within the memory device instructs the refresh target banks BA2 and BA3 to perform the refresh operation. In this horizontal access 1020, an active command ACT is inputted along with a bank address BA=0 and a row address RA=0, the page areas of BA0 and RA0 are activated, then a read command RD is inputted along with a bank address BA=0 and a column address CA=0, and the data is read. Similarly, a active command ACT is inputted along with a bank address BA=1 and a row address RA=0, the page areas of BA1 and RA0 are activated, a read command RD is inputted along with a bank address BA=1 and a column address CA=0, and the data is read. In the horizontal access, these operations are repeated for a certain period of time. In the meantime, the refresh operation is repeated in the banks BA2 and BA3.
The operations similar to those described above are carried out in the horizontal access 1021 as well. Specifically, the background refresh command BREN (a reference numeral 65 in the figure) is inputted along with BA0, 1 as the refresh bank information SA (a reference numeral 66 in the figure), and the refresh operation is performed in the banks BA0, 1. In parallel with this refresh operation, and an active command and a read command are repeatedly inputted, whereby the horizontal access operation is performed on the banks BA2, 3. During the rectangular access 1024, the background refresh operation is not performed.
The abovementioned background refresh command BREN corresponds to the first code. Also, the active command ACT and read command RD or write command WT (not shown) correspond to the second code.
Specifically, in the horizontal access a part of banks are repeatedly accessed during a certain period of time in accordance with the size of the access target image. However, the time period of the horizontal access varies, and the horizontal access occurs randomly. Therefore, it is required that the refresh operation be executed on the desired number of addresses in the refresh target bank during the horizontal access. For example, in the case in which the refresh operation needs to be performed on an address N during a horizontal access period T, if T÷τ≧N is satisfied where τ is a cycle time required in a single refresh operation, the refresh operation may be executed N times on one block (one word line). However if T÷τ≧N is not satisfied, a plurality of blocks (a plurality of word lines) are subjected to a single refresh operation simultaneously, whereby the number of N needs to be reduced effectively. The number of blocks that are subjected to the refresh operation simultaneously is the refresh block count RBC.
Furthermore, if the size of access target data is larger than predetermined size, the horizontal access period is extended by a certain amount. In this case, the number of commands issued can be reduced by repeating the refresh operation a number of times on a single background refresh command BREN. In this case, the number of times the refresh can be executed during the horizontal access period T is T÷τ, which is the refresh burst length RBL. By specifying the refresh burst length RBL when the horizontal access is started, the refresh cycle is ended at the point of time when the horizontal access period T is ended, thus the memory device, immediately thereafter, can issue an active command to enter the cycle of the normal memory operation.
Returning to
Finally,
As described above, in the background refresh of the present embodiment, the refresh bank information SA indicating the refresh target bank, the refresh burst length RBL, and the refresh block count RBC are inputted along with the command BREN or the register set command EMRS so as to flexibly respond to the occurrence and period of random horizontal accesses.
Incidentally, the memory controller can cause the memory device to execute the background refresh operation a number of times by setting the refresh burst length RBL, but once the refresh operation is started, it is inconvenient if the number of refresh operations corresponding to the refresh burst length RBL cannot be changed. Therefore, as will be described hereinafter, in the present embodiment, the refresh burst length RBL can be increased by addition or reset to obtain new burst length RBL, or the refresh operation can be stopped. In order to flexibly respond to random horizontal accesses, the background refresh command can be issued beforehand by means of a function of adding burst length RBL. The function of resetting the burst length can be used in new horizontal access is generated. Moreover, the command for stopping the refresh operation is effective when the refresh burst length RBL that has been set once is excessively long.
Further, in the present embodiment, a refresh-all command for executing the refresh operation on all remaining addresses can be used. Accordingly, the memory area without effective data can be forcibly caused to perform the refresh operation to reset a refresh counter. This will be described hereinafter.
In
As described above, the refresh burst length RBL and the refresh block count RBC may be set each time along with the command BREN, or set into the mode register beforehand. By setting the refresh burst length RBL, and the refresh block count RBC into the mode register, the refresh burst length RBL and the refresh block count RBC do not have to be set each time along with the command BREN.
As shown in
On the other hand, as shown in
In the case of
In the case of
The invention described in the abovementioned Patent Literature 6, U.S. Patent Application Publication No. US2005/0265104A1, corresponds to
Above has described the overview of the background refresh function. A configuration of the memory device for realizing this function is described hereinafter.
[Memory Device with Background Refresh Function]
The memory device 86 has four banks 92 in addition to the abovementioned control circuit. Each of the banks has a core 1086 having a memory cell array, a decoder and a sense amplifier, a core control-circuit 1085 for controlling the core, a refresh address counter 1083 for generating a refresh address (row address) REF_RA of each bank, and an address latch circuit 1084 for latching the address az<13:0> supplied from outside or any of the refresh addresses REF_RA. Although the figure shows only a detailed configuration of the bank Bank0, other banks Banks 1, 2 and 3 have the same configuration.
The core control circuit 1085 of each bank activates the internal core if the bank selection signal bnkz<0:3> is in a selected state, in response to the active pulse signal actpz that is generated in response to the active command ACT. In this case, the address latch circuit 1084 latches the address az<13:0> supplied from the outside, supplies the address to the decoder within the core 1086. In response the refresh pulse signal refpz generated in response to the background refresh command BREN, the core control circuit 1085 activates the internal core and causes the core to perform the refresh operation, if the refresh bank selection signal ref_bnkz<0:3> is in a selected state. In this case, the address latch circuit 1084 latches the refresh address REF_RA of the refresh address counter 1083, supplies the address to the decoder within the core.
[Example of Configuration of Banks of Memory Device]
On the other hand, at the time of the background refresh, a pointer 1112 is activated by the refresh pulse signal refpz when the refresh bank selection signal ref_bnkz<0:3> is in the selected state, the word driver 1113 corresponding to the pointer in the selected state drives the word line, and the refresh operation is performed by the memory cell area 1114 and the sense amplifier 1116. Once the refresh operation is ended, the pointer 1112 changes the next pointer to the selected state. In this manner, every time the refresh operation is ended, the group of pointers 1112 moves the selected positions successively so that the word lines within the memory cell area can be driven sequentially.
In the example shown in
On the other hand,
It should be noted that in the example shown in
As shown in
[Refresh Bank Decoder, Core Control Circuit, and Address Latch Circuit]
Next, specific examples of the refresh bank decoder, core control circuit and address latch circuit shown in
Bank selected by BA<1>=0 and BA<0>=0 is Bank 0
Bank selected by BA<1>=0 and BA<0>=1 is Bank 1
Bank selected by BA<1>=1 and BA<0>=0 is Bank 2
Bank selected by BA<1>=1 and BA<0>=1 is Bank 3
A second example of a refresh bank decoder 1082(2) shown in
In the case in which a combination of banks configuring one line in the horizontal direction is Bank 0, 1 (or Bank 2, 3), it is preferred that the first example be used for the background refresh that is performed at the time of horizontal access. On the other hand, in the case in which a combination of banks configuring one line in the horizontal direction is Bank 0, 2 (or Bank 1, 3), it is preferred that the second example be used as the background refresh. The combination of banks in the horizontal direction depends on the memory mapping of the memory system that uses the memory. Therefore, the memory device needs to have the refresh bank decoder of the first or second example, depending on the memory mapping.
(1) When modez<1:0>=1, 1, one bank that is specified by the bank address terminals BA<1> and BA<0> is selected. Specifically, only one bank is selected from the four banks.
(2) When modez<1:0>=1, 0, a combination of two banks, i.e. Banks 0, 1 or Banks 2, 3 that are selected by the bank address terminal BA<1>, is selected.
(3) When modez<1:0>=0, 1, a combination of two banks, i.e. Banks 0, 2 or Banks 1, 3 that are selected by the bank address terminal BA<0>, is selected.
(4) When modez<1:0>=0, 0, all of the refresh bank selection signals ref_bnkz<0:3> enter the selected stated. Therefore, once the refresh command BREN is inputted, the refresh is executed in the four banks.
In the refresh bank decoder 1082(4), two NAND gates to which the bank address baz<0> is inputted are activated when modez<0>=1, pre-decode signals baOx, z become 1 or 0, and banks are selected in a combination of the refresh bank selection signals ref_bnkz<0, 2>, <1, 3>. On the other hand, two NAND gates to which the bank address baz<1> is inputted are activated when modez<1>=1, a pre-decode signals ba1x, z become 1 or 0, and banks are selected in a combination of the refresh selection signal ref_bnkz<0, 1>, <2, 3>.
In the case of this example, in the system that has the combination of Banks 0, 1 (Banks 2, 3) configuring the one line in the horizontal directions, the mode register set value may be set to modez<1:0>=1, 0. Also, in the system that has the combination of Banks 0, 2 (Banks 1, 3) configuring the one line in the horizontal direction, the mode register set value may be set to modez<1:0>=0, 1. Furthermore, in the system in which the refresh is performed in units of banks, modez<1:0>=1, 1 may be set, and in the system in which the refresh is performed on all banks simultaneously as in the conventional manner, modez<1:0>=0, 0 may be set.
The refresh bank decoder 1082(6) inputs the bank selection signals bnkz<3:0> that are generated from the bank addresses BA<1:0> by the normal bank decoder, and then generate refresh bank selection signals ref_bnkz<0:3>
First of all, as shown in a memory map 1170, in the system in which the combination of the banks configuring one line in the horizontal direction is Banks 0, 1 (or Bank 2, 3), a bank selection signal bnkz<0> is selected if BA<1>=0 and BA<0>=0 (bankz<0>=High, and the rest is Low), and Bank 0 and Bank 1 are selected. If BA<1>=1 and BA<0>=1, a bank selection signal bnkz<3> is selected (bankz<3>=High, the rest is Low), and Bank 2 and Bank 3 are selected.
On the other hand, as shown in a memory map 1171, in the system in which the combination of the banks configuring one line in the horizontal direction is Banks 0, 2 (or Bank 1, 3), a bank selection signal bnkz<1> is selected if BA<1>=0 and BA<0>=1, and Bank 1 and Bank 3 are selected. If BA<1>=1 and BA<0>=0, a bank selection signal bnkz<2> is selected, and Bank 0 and Bank 2 are selected.
(1) Bank 0 and Bank 1 are selected if A<3>=0, A<2>=0, A<1>=1 and A<0>=1,
(2) Bank 2 and Bank 3 are selected if A<3>=1, A<2>=1, A<1>=0 and A<0>=0,
(3) Bank 0 and Bank 2 are selected if A<3>=0, A<2>=1, A<1>=0 and A<0>=1,
(4) Bank 1 and Bank 3 are selected if A<3>=1, A<2>=0, A<1>=1 and A<0>=0, and
(5) Bank 0, Bank 1, Bank 2 and Bank 3 are all selected if A<3>=1, A<2>=1, A<1>=1 and A<0>=1.
(6) If any of A<3:0> is 1, one corresponding bank is selected. In this case, the bank address terminal BA<1:0> or the rest of the address terminals A<13:4> are ignored.
First of all, this core control circuit 1085 has a timing control circuit 1190 that generates various timing signals in response to an active pulse signal actpz, refresh pulse signal refpz, and pre-charge pulse signal prepz, and a refresh control circuit 1191 that controls a refresh in response to the refresh pulse signal refpz. An RS flip-flop FF1 constituted by two NAND gates latches an active state, and an RS flip-flop FF3 latches a refresh state. A set input 1192 and a reset input 1193 are inputted to the RS flip-flop FF1. Furthermore, a set input 1194 and a reset input 1195 are inputted to the RS flip-flop FF3.
In the figure, an active state signal rasz shows an active state at H level, and also shows a pre-charge state at L level. An equalizing signal eqlonz equalizes a pair of bit lines of the memory cell array at the H level, and cancels the equalization at the L level. A word line activation signal wlonz activates a word line at the H level, and deactivates the word line at the L level. A sense amplifier activation signal saonz activates a sense amplifier at the H level, and deactivates the sense amplifier at the L level. The active pulse signal actpz is brought to the H level by the command decoder in response to an active command ACT. The refresh pulse signal refpz is brought to the H level when a refresh command is inputted. The pre-charge pulse signal prepz is brought to the H level when a pre-charge command PRE is inputted. A bank selection signal bnkz<#> is an output signal of the normal bank decoder and specifies a bank that executes an active or pre-charge operation when Bnkz<#> is brought to the H level. A reference numeral “#” is the number of a bank. The refresh bank selection signal ref_bnkz<#> is an output signal of the refresh bank decoder, and is used to specify a bank that executes a refresh operation when ref_bnkz<#> is brought to the H level.
On the other hand, in the state in which the RS flip-flop FF3 is set, a refresh active state signal ref_rasz is also brought to H level. The refresh pre-charge pulse ref_prepz is brought to the H level from a rising edge of the sense amplifier activation signal saonz by an AND gate 1196 after a lapse of a delay time of a delay circuit DELAY-4, and the RS flip-flops FF3 and FF1 are reset. By resetting the RS flip-flop FF1, the active state signal rasz is brought to the L level, the word line activation signal wlonz is also brought to the L level, and the word line is brought to the L level. Then, the equalizing signal eqlonz is brought to the H level after a lapse of a delay time of DELAY-1, the pair of bit lines of the memory cell is then equalized, and the pre-charge of the memory cell array is completed. As a result, one cycle of pre-charge operation is ended.
It should be noted that in the normal operation, once the active pulse signal actpz corresponding to the active command ACT received at the clock number 9 is brought to the H level, the RS flip-flop FF1 is set, the equalizing signal eqlonz is brought to the L level, the signals rasz, wlonz and saonz are brought to the H level sequentially, and the memory cell array is activated. Then, once the pre-charge pulse prepz corresponding to the pre-charge command PRE is brought to the H level, the RS flip-flop FF1 is reset, the signals rasz, wlonz and saonz are brought to the L level sequentially, the equalizing signal eqlonz is then brought to the H level, and the memory cell array is pre-charged. This is one cycle of normal operation. At the time of the normal operation, the refresh control circuit 1191 is not operated.
As described above, the refresh operation is constituted by the active operation and the pre-charge operation, while the normal operation is constituted by the active operation, the read or write operation, and the pre-charge operation. It should be noted that the illustration of a read command or a write command is omitted in
Further, as shown in the timing chart of
[Refresh Burst Control]
Next, characteristic refresh burst control of the background refresh operation of the present embodiment is described. In the refresh burst control, the memory device repeatedly performs a refresh operation a number of times corresponding to the refresh burst length in response to a single background refresh command. Accordingly, as shown in
Once the background refresh command BREN is received at the clock number 0, the memory device repeatedly executes refresh operation four times on Banks 0, 1. Furthermore, the memory controller issues an active command ACT to Banks 2, 3 at clock numbers 2, 4, issues a read command RD at clock numbers 5, 7, and further issues a pre-charge command PRE at clock numbers 8, 9. Similarly, an active command ACT is issued to Banks 2, 3 at clock numbers 11, 13, and a read command RD and a pre-charge command PRE are also issued. In response to this, the memory device executes an active operation on Banks 2, 3. The active operation performed on Banks 2, 3 is executed in parallel with the refresh operation performed on Banks 0, 1.
By specifying the refresh burst length RBL, the four refresh operations are completed at a clock number 16, and an active command ACT can be issued to Banks 0, 1 immediately after a clock 19.
As shown in a table 1231T in the figure, refresh burst lengths RBL=1 through 16 corresponding to 4-bit information inputted from address terminals az<7:4> are set in the refresh burst length register 1231, the refresh burst lengths being shown in the table 1231T. This setting is performed when the refresh pulse signal refpz and refresh bank selection signal ref_bnkz<#> that are generated in response to the background refresh command BREN are equal to H.
The refresh burst length counter 1230 is set when refresh pulse signal refpz=H and refresh bank selection signal ref_bnkz<#>=H. Every time one cycle of refresh operation is ended, the refresh control circuit 1191 outputs an internal refresh pulse signal int_refpz (=H) for directing the next refresh operation, in response to which the refresh burst length counter 1230 increments a count value. Then, when the count value of the counter 1230 matches the burst lengths RBL that are set in the refresh burst length register 1231, the refresh burst end detection circuit 1232 outputs a refresh burst end signal rb_endz (=H). In response to this, the refresh control circuit 1191 resets the RS flip-flop circuit that latches a refresh state, and stops outputting the subsequent internal refresh pulse signal int_refpz and refresh pre-charge pulse signal ref_prepz.
The refresh burst end detection circuit 1232 inputs, from the mode register 96, signals modez<7:4> indicating the refresh burst length, and compares these signals with the count value of the refresh burst length counter 1230. The other configurations are the same as those shown in
In order to control the repetition of the refresh operation, the refresh control circuit 1191 brings the internal refresh pulse signal int_refpz (arrows 1251, 1252) to the H level (pulse width of DELAY-0) after a lapse of a delay time of DELAY-5 once the equalizing signal eqlonz is brought to the H level at the end of the refresh cycle. This internal refresh pulse signal int_refpz sets the RS flip-flop FF1 (arrow 1253), and directs the start of the next refresh cycle. This internal refresh pulse signal int_refpz increments the refresh counter as described above.
Then, in order to stop the refresh operation, in the refresh control circuit 1191, when the refresh burst end signal rb_endz (arrow 1254) is brought to the H level when the refresh cycle corresponding to the burst length is ended, and when the refresh pre-charge pulse signal ref_prepz is brought to the H level when the refresh operation cycle is ended, the RS flip-flop FF2 is reset by the reset input 1195, and the refresh state signal ref_statez is reset to L. As a result, the output of an AND gate 1197 is fixed to the L level, and the internal refresh pulse signal int_refpz that directs the start of the next refresh cycle is no longer outputted.
The detailed operations of the core control circuit shown in
The refresh burst length register latches the signals of the address terminals az<7:4> in response to the refresh pulse signal refpz, and outputs the latched rblrz<3:0> indicating the refresh burst length to the refresh burst end detection circuit 1232.
The refresh burst end detection circuit 1232 compares the counter values rblcz<3:0> with the refresh burst lengths rblrz<3:0>, and, when both match, outputs a refresh burst end signal rb_endz. The subsequent refresh operation is stopped by this refresh burst end signal rb_endz.
A refresh pulse signal refpz is outputted by the refresh command BREN, in response to which the values of the address terminals A<7> through A<4> are incorporated into the refresh burst length registers 1231 of the refresh target banks, Banks 0 and 1. The rblrz<3:0>=0011b in the figure is an example in which the burst length RBL=4. At the same time, the counter values of the refresh burst length counters 1230 of the Banks 0 and 1 are reset to rblcz<3:0>=0000b. Moreover, the refresh state signal ref_statez is set to the H level by the RS flip-flop FF2 within the refresh controller circuit 1191.
At this moment, the RS flip-flop FF1 within the timing control circuit 1190 is also set, the active state signal rasz=High is set, and the refresh cycle operation is started. At the same time, the timing control circuit 1190 sets the equalizing signal eqlonz to Low, the word line activation signal wlonz to High, and the sense amplifier activation signal saonz to the H level as with
After a lapse of the delay time DELAY-4 since the sense amplifier activation signal saonz has been inputted, the refresh pre-charge signal ref_prepz is outputted by the AND gate 1196, the RS flip-flop FF1 is reset, the active state signal rasz is set to Low, the equalizing signal eqlonz is set to High, and the pre-charge operation is started. At this moment, the value of the refresh burst length register 1231 is different from the value of the refresh burst length counter 1230 (rblrz<3:0>≠rblcz<3:0>), thus the refresh end signal rb_endz remains Low.
The refresh control circuit 1191 outputs the internal refresh pulse signal int_refpz via the AND gate 1197 after lapse of the delay time DELAY-5 since the equalizing signal eqlonz=High has been set, sets the RS flip-flop FF1, and starts the subsequent refresh operation. At this moment, the value of the refresh burst length counter is counted up to become 0001b. Moreover, the address latch circuit 1084 (
Once the third internal refresh pulse signal int_refpz is outputted, and the fourth refresh operation is started, the value of the refresh burst length counter is counted up to become rblcz<3:0>=0011b. At this moment, the value of the refresh burst length register rblrz<3:0> and the value of the refresh burst length counter rblcz<3:0> are equal to each other (rblrz<3:0>=rblcz<3:0>=0011b), and the refresh burst end detection circuit 1232 sets the refresh burst end signal rb_endz=High. Once the fourth refresh operation is ended, the pre-charge signal ref_prepz is outputted and the active state signal rasz becomes Low. However, the refresh end signal rb_endz=High, thus the RS flip-flop FF2 is reset by the reset input 1195, as a result of which the refresh state signal ref_statez transits to a Low state. When the equalizing signal eqlonz is set to High as the pre-charge operation is performed, the internal refresh signal int_refpz for starting the subsequent refresh operation is not outputted according to ref_statez=Low, thus the four refresh burst operations are ended.
In the example shown in
[Refresh Burst Stop Control]
The refresh burst function inputs the background refresh command once and repeats the fresh cycles by the specified burst length, thus the number of inputs of the command can be reduced and the access efficiency can be enhanced. However, if the burst length is longer, and access is not allowed to the bank until the background refresh operation that has been started once is ended, the flexibility of the memory control is lost. For this reason, the memory device of the present embodiment has a refresh burst stop function.
The stop command STOP is specified by, for example, a refresh command (e.g., /CS=L, /RAS=L, /CAS=L, /WE=H) and a signal of an address terminal that is obtained at the time of command input. Specifically, the stop command has the same command signal as the refresh command and is distinguished by the address terminal signal. Alternatively, a pre-charge command (e.g., /CS=L, /RAS=L, /CAS=H, /WE=L) is used as the stop command STOP.
The refresh state control circuit 1191B sets the refresh state signal ref_statez to the H level in response to the refresh pulse signal refpz, and resets the refresh state signal ref_statez to the L level in response to the refresh stop pulse signal ref_stoppz. By means of this refresh state signal ref_statez, the start and stop of refresh performed by the refresh control circuit 1191 are controlled. Also, the refresh control circuit 1191 ends the refresh operation as described above when a refresh cycle is ended by the refresh burst end signal rb_endz indicating the end of the refresh cycle, the number of the refresh cycles corresponding to the burst length.
In either one of the refresh state control circuits 1191B, the RS flip-flop FF2 is set by the refresh pulse signal refpz=H to obtain the refresh state signal ref_statez=H, and is reset by a NAND gate 1321 to obtain the refresh state signal ref_statez=L in response to a refresh burst end signal rb_ends<#> H and the refresh pre-charge pulse signal ref_prepz=H. The above is the normal refresh burst operation.
Then, in
On the other hand, in
Moreover, the difference with
When the active operation is ended, the refresh pre-charge pulse signal ref_prepz=H is outputted after the del-ay time DELAY-4 in response to the sense-amplifier activation signal saonz=H, the RS flip-flops FF1 and FF3 are reset, and the active state signal rasz and the refresh active state signal ref_rasz are brought to the L level. Accordingly, the pre-charge operation is started. After a lapse of the delay time DELAY-5 since the equalizing signal eqlonz for starting the pre-charge operation has been inputted, the internal refresh pulse signal int_refpz=H for directing the start of the subsequent refresh cycle is outputted, whereby the subsequent refresh cycle is started.
Then, the stop command STOP is inputted during the active operation of the third refresh cycle. In response to this, the refresh stop pulse signal Ref_stoppz=H is outputted from the command decoder, and the refresh state control circuit 1191B outputs the refresh state signal ref_statez=L. At the timing that indicates the end of the active operation in the third refresh cycle, i.e., the timing that comes after a lapse of the delay time DELAY-4 since the sense amplifier activation signal saonz=H has been inputted, the AND gate 1332 outputs the refresh pre-charge pulse signal ref_prepz=H for directing the start of pre-charge, on the basis of the refresh active state signal ref_rasz=H. Accordingly, the pre-charge operation in the third refresh cycle is executed reliably.
In response to the refresh pre-charge pulse signal ref_prepz=H, the RS flip-flops FF1 and FF3 are reset, and the equalizing signal eqlonz=H is set, whereby the pre-charge operation is started. Then, at the timing that comes after a lapse of the delay time DELAY-5, the arbitrating circuit 1334 does not output the internal refresh pulse signal int_refpz=H for directing the start of the subsequent refresh cycle, on the basis of the refresh state signal ref_statez=L.
In this manner, according to the core control circuit described above, once the stop command STOP to be inputted at arbitrary timing is generated using the refresh state signal ref_statez and the refresh active state signal ref_rasz, the pre-charge operation of the refresh cycle in progress is ended reliably, and a new re-fresh cycle is prohibited from starting after the stop command STOP is inputted.
[Countdown Refresh Burst Control]
Next, an embodiment in which the refresh burst control is performed using a down counter is described. In the example described above, the refresh burst counter is counted up for every refresh cycle, but in the following embodiment each refresh burst counter is counted down for every refresh cycle, andwhen all count valuesof the refresh burst counters become 0 the refresh burst operation is ended. Therefore, all of the refresh burst counters are reset to zero in response to the stop command inputted during the background refresh operation, whereby stop control can be performed.
By using this down counter, a new background refresh command can be inputted before the refresh burst operation is ended, so that control for overwriting the refresh burst counter onto burst length that is specified by a new command, and control for adding the burst length specified by a new command to the current refresh burst counter can be performed.
Furthermore, the following embodiment describes that, although the refresh address counter is incremented or decremented in every refresh cycle, control is performed for returning the refresh address counter from the existing count value to the initial value by means of a refresh-all command for integrally refreshing all of the remaining refresh addresses.
As with the circuit diagram of
A refresh burst operation is started by means of the refresh pulse signal refpz corresponding to a background refresh command, the down signal downz is outputted for every refresh cycle, whereby the refresh burst length counter 1230 is down counted, and the internal refresh pulse signal int_refpz for directing the start of the subsequent refresh cycle is outputted. The refresh control circuit 1191 repeats the above-described refresh cycle operation during a period in which all of the count values rblcz<3:0> of the refresh burst length counters are not zero (L level). If the all count values rblcz<3:0> become zero (L level), the refresh control circuit 191 does not output the internal refresh pulse signal int_refpz for directing the start of anew refresh cycle. If the all count values rblcz<3:0> are changed to zero (L level) by the stop command from the address terminal A<5>, the refresh control circuit 1191 also does not output the internal refresh pulse signal int_refpz anymore.
The core control circuit 1085 shown in
Then, the refresh control circuit 1191 sets the refresh interval signal refitvalx to H after a lapse of a delay time DELAY-6 after the active state signal rasz<#> is brought to the L level, and outputs the internal refresh pulse signal int_refpz for directing the start of the subsequent refresh cycle. Furthermore, the refresh control circuit 1191 outputs the down signal downz=H of the pulse width of a delay time DELAY-7 in response to a word line drive signal wlonz<#>=H, and counts down the count value of the refresh burst length counter 1230.
An output of a NAND gate 1400 is brought to the L level when all of the refresh burst length count values rblcz<3:0>=L and when the refresh-all signal rblcallz=L, whereby the output of the internal refresh pulse signal int_refpz is prohibited via an AND gate 1401. In the normal state, the refresh-all signal rblcallz=L, thus when all of the refresh burst length count values rblcz<3:0> become L during the refresh burst operation, the output of the internal refresh pulse signal int_refpz is prohibited. Moreover, during a period where the refresh-all signal rblcallz corresponding to the refresh-all command is H, the internal refresh pulse signal int_refpz is outputted regardless of the refresh burst length count values rblcz<3:0>.
It should be noted that the address-terminal A<10> shown in
The refresh burst length register 1231 incorporates the refresh burst length from the address terminals A<3:0> into latch circuits 1410, 1412 in response to a refresh pulse signal refpz. Gates 1411, 1413 outputs the latched values directly as the refresh burst length register values rblrz<3:0>, since normally a down signal downz and a self refresh mode signal srefz are both in the L level. Furthermore, the refresh burst length register 1231 sets the register values rblrz<3:0> to 0001 in response to the self refresh signal srefz=H that directs the conventional refresh operation of the SDRAM.
The refresh burst length counter 1230 has a down counter 1414 that incorporates the register value rblrz<3:0> in response to the refresh pulse signal refpz=H, and down counts the register values in response of the down signal downz=H. The down counter 1414 resets all rblcz<3:0> to L in response to the refresh pulse signal refpz=H and address terminal A<5>=H corresponding to the stop command (in response to the refresh stop command REFSTOP in the example shown in
The refresh address comparison circuit 1370 has an RS flip-flop FF4 that is set in response to the refresh-all command REFALL, and a group of NAND gages 1432 for detecting whether all of the refresh addresses ref_az<13:0> are H. In the normal state, the RS flip-flop FF4 is reset, a node 1430 is in the H level, and the refresh-all signal rblcallz is L. Then, the RS flip-flop FF4 is set in response to the refresh-all command REFALL, whereby the node 1430 is brought to the L level, and the refresh-all signal rblcallz becomes H. During a period where rblcallz=H, the refresh operation is repeated by the refresh control circuit 1191, and the refresh address counter 1083 is down counted every time the sense amplifier activation signal saonz becomes H. When all of the refresh addresses ref_az<13:0> are changed from L to H, the NAND group 1432 detects this change, brings the node 1431 to the H level, and sets the refresh-all signal rblcallz to L. In response to this, the refresh control circuit 1191 stops the refresh operation, and the RS flip-flop FF4 is reset. Accordingly, a refresh-all operation for refreshing all of the remaining addresses within the refresh address counter 1083 is ended.
Then, the core is subjected to the active operation, and the refresh control circuit 1191 outputs the down signal downz=H via an AND gate 1430 in response to the sense amplifier activation signal saonz=H. In response to this, the refresh burst length counter 1230 shown in
Then, once the abovementioned refresh cycle is repeated three times, the count values rblcz<3:0> of the refresh burst length counter becomes 0000b, then the output of the NAND gate 1400 of the refresh control circuit 1191 is brought to the L level, and subsequent internal refresh pulse signals int_refpz are not outputted by the AND gate 1401. In this manner, the refresh operation of the burst length 3 is ended.
The refresh addresses ref_az<13:0> of the refresh address counters 1083 (
In this manner, the function of adding the refresh burst length by means of a new background refresh command is provided in the refresh burst control, whereby the memory controller can preferentially issue the background refresh command in order to perform the background refresh operation in the future.
In this manner, the function of rewriting the refresh burst length by means of a new background refresh command is provided in the refresh burst control, whereby the memory controller can cancel the background refresh operation that has been started once, to start new background refresh operation. By adding and rewriting the burst length RBL by means of the new background refresh command as shown in
[Active and Refresh Interlocking Control]
Next, control for interlocking an active operation and a refresh operation is described. In the embodiment described above, the active command ACT in the normal memory operation and the command BREN in the background refresh operation are different commands. The memory controller issues these commands separately, and thereby causes the memory device to execute the normal memory operation and the background refresh operation.
In the following embodiment, on the other hand, setting is performed so as to execute the background refresh operation in conjunction with an active command in the mode register or the like beforehand, whereby the memory device performs a normal active operation in a selected bank and a refresh operation in a refresh target bank in response to the input of the active command for the normal memory operation. Such a function is provided so that the memory controller does not have to issue the background refresh command.
Specifically, as shown in the table in the figure, in response to the values of the bank addresses BA<1:0> that are inputted along with the active commands ACT, the memory device executes the refresh operation in a specific bank. More specifically, if the BANK0 is selected by the active command, the refresh operation is performed in the BANK3, if the BANK1 is selected by the active command, the refresh operation is performed in the BANK2, if the BANK2 is selected by the active command, the refresh operation is performed in the BANK1, and if the BANK3 is selected by the active command, the refresh operation is performed in the BANK0. By using such combinations, even in either the memory mapping 1170 or 1171 shown in
In the present embodiment, the background refresh operation is executed once in response to the active command ACT. Therefore, the refresh burst length RBL is fixed to 1.
The mode value modez=H/L is set in an incorporated register beforehand by the mode register set command EMRS. Alternatively, the mode value modez=H/L is inputted from a predetermined external terminal. Therefore, according to the example described above, preferably the mode value modez=H is set in the case of a horizontal access, and the background refresh operation is performed in conjunction with the active command ACT. In the case of a rectangular access, preferably the mode value modez=L is set, and the background refresh operation is prohibited.
In the refresh selection bank (ref_bnkz<#>=H), on the other hand, the RS flip-flop FF1 is set via a NAND gate 1521 in response to the active pulse signal actpz =H, and the active state signal rasz is brought to the H level, whereby the core is subjected to the active operation. At the same time, the RS flip-flop FF3 within the refresh control circuit 1191 is also set via a NAND gate 1522 in response to the active pulse signal actpz=H, and the refresh active state signal ref_rasz is set to the H level. The refresh operation is started by setting the active state signal rasz to the H level, and then the RS flip-flop FF1 is reset by the refresh pre-charge pulse signal ref_prepz=H brought in response to the sense amplifier activation signal saonz=H, whereby the pre-charge operation is performed. At the same time, the RS flip-flop FF3 is reset.
As described above, in response to the normal active command, the normal active operation and the background refresh operation are executed in parallel in accordance with a combination of banks that is set beforehand.
[Control using Refresh Block Count]
Next, control that is performed using the refresh block count RBC according to the present embodiment is described. In the background refresh operation of the present embodiment, in addition to the refresh burst length RBL that defines the number of refresh cycles, the number of blocks (the number of word lines) RBC that are activated simultaneously in a single refresh cycle can be set.
By increasing the refresh block count RBC, a refresh can be executed on a larger number of refresh addresses simultaneously. Therefore, when a period in which the background refresh can be performed is short, it is desired that the refresh block count RBC be large. On the other hand, if the refresh block count RBC is increased, the refresh operation is executed on a larger number of word lines simultaneously, and the amount of power that is consumed instantly is increased. Therefore, if the period in which the background refresh can be performed is long, it is desired that the refresh block count be small as much as possible. Thus, the memory controller sets the refresh block count RBC to an optimal value in accordance with the period in which the background refresh can be performed and the conditions of the power consumption.
The address latch circuit 1084 has a latch group 1564 that latches a non-inverted signal and inverted signal of an upper 2-bit address out of 14-bit row address, and a latch group 1565 that latches lower 12-bit address. The latch group 1564 latches non-inverted signals of external addresses az <13> and <12> and inverted signals obtained by inventors 1566 and 1567, in response to an active pulse signal actpz. Similarly, the latch group 1564 latches non-inverted signals of refresh addresses REF_A <13> and <12> and inverted signals obtained by invertors 1568 and 1569, in response to a refresh pulse signal refpz. However, the non-inverted signals and inverted signals of the refresh address REF_A <13> and <12> are caused to degenerate to the H level by NAND gates 1560 through 1563 in response to signals modez <0> and <1> set in the mode register. Accordingly, the word lines of a plurality of memory blocks can be driven simultaneously.
The operations shown in
First of all, in the case in which RBC=1, modez<0>=modez<1>=0,
raz<13> and REF_A<13> are in-phase, rax<13> and REF_A<13> are reversed-phase, and
raz<12> and REF_A<12> are in-phase, rax<12> and REF_A<12> are reversed-phase.
One of the four Blocks RBLK is selected by the pre-decoder circuit 1086D, whereby one word line WL of the selected block is activated.
Next, in the case in which RBC=2, modez<0>=1, modez<1>=0, raz<13> is set to High, rax<13> is also set to High, raz<12> and REF_A<12> are in-phase, and rax<12> and REF_A<12> are reversed-phase. Then, two of the four Blocks RBLK are selected by the pre-decoder circuit 1086D, whereby two word lines WL of the selected blocks are activated.
Finally, in the case in which RBC=4, modez<0>=1, modez<1>=1, raz<13> is set to High, rax<12> is also set to High, raz<13> is set to High, and rax<12> is also set to High. Then, four of the four Blocks RBLK are selected by the pre-decoder circuit 1086D, whereby four word lines WL of the selected blocks are activated.
The above is the explanation of the memory device having the background refresh-function. Next, the memory controller that controls the memory device and causes the memory device to perform the background refresh operation is described.
[Memory Controller Controlling Background Refresh]
In order to cause the memory device to execute the background refresh function, the memory controller needs to provide the background refresh command BREN, refresh bank information SA, and refresh burst length RBL to the memory device. Furthermore, it is preferred that the memory controller provide the refresh block count RBC to the memory device. Hereinafter, the memory controller that controls a background refresh is described.
On the basis of the access request and various information sent from the image processing device 81, the memory controller 82 outputs the background refresh command, refresh bank information SA, refresh burst length RBL, and the refresh block count RBC to the memory device 86 in the case of a horizontal access, and further outputs an active command CMD, a bank address BA, a row address RA, a read or write command CMS, a bank address BA, and a column address CA that correspond to the horizontal access, to the memory device 86. Further, the memory controller 82 outputs similar signals corresponding to a rectangular access to the memory device 86. Then, the memory controller 82 outputs write data DQ to the memory device 86 in the case of a write access, and inputs read data DQ from the memory device 86 in the case of a read access.
In such memory map 12, an upper left pixel corresponds to an image address of ADR=0x00, POSX, POSY=0, 9. A right end pixel in the first row corresponds to an image address of ADR=0x03F, POSX, POSY=0, 63. A left end pixels in the 32nd row corresponds to an image address of ADR=0x7C0, POSX, POSY=31, 0. In this case, the image address ADR can be expressed by the position information POSX, POSY of the upper left pixels in an access area. Specifically, for the 12 bits of image addresses ADR[11:0],
POSY[5:0]=ADR[11:6], POSX[5:0]=ADR[5:0].
Therefore, the memory controller 82 can obtain the position information POSX and POSY of the upper left pixel of the access area from the image addresses ADR received from the image processing device 81. It should be noted that in the example shown in
Next, the size in a horizontal direction of the access area, SIZEX, and the size in a vertical direction, SIZEY, are supplied by the image size signal SIZE and access type signal ATYP respectively. Specifically, SIZEX=SIZE and SIZEY=ATYP. In the case of a horizontal access, SIZEY=ATYP=0—0000b is supplied, and in the case of a rectangular access, the value of SIZEY=ATYP is any value other than 0. Therefore, the memory controller 82 can discriminate whether an access is a horizontal access or rectangular access, based on whether the value of the access type signal ATYP is 0 or not.
Also, on the basis of the memory map 12, the memory controller 82 can obtain the bank address BA and row address RA of the front pixel in the access area from the position information POSX, POSY of the upper left pixel in the access area. The memory controller 82 can discriminate whether to access a plurality of banks, on the basis of the position information POSX and POSY of the upper left pixel of the access area, and the size information SIZE and ATYP.
Furthermore, the memory controller 82 can obtain the number of pixels accessing the memory device, on the basis of the size information SIZE and ATYP, and can further determine that the next memory access request is not generated for a period of time corresponding to the number of clock cycles required for transferring at least the data on the number of pixels to the image processing device. The memory controller 82 can further obtain the refresh burst length RBL in a background refresh on the basis of such period of time, and can also obtain the refresh block count RBC.
The horizontal access determination section 1610 uses a first comparator CMP1 to determine whether the access type signal ATYP indicating the size in a vertical direction SIZEY is “0” or not. The output of the first comparator CMP1 is “1” if ATYP=0. The horizontal access determination section 1610 further uses a second comparator CMP2 to determine whether the size signal SIZE indicating the size in a horizontal direction SIZEX exceeds the number of clocks MEMREF in a single refresh cycle. The output of the second comparator CMP2 is “1” if SIZE≧MEMREF. Therefore, if the outputs of both comparators are “1”, an AND gate outputs a background refresh enable signal “1”, and requests the controller 1615 to issues a background refresh command. The number of clocks MEMREF described above is set in, for example, a register within a memory controller.
Next, the refresh burst length RBL calculator 1611 calculates the refresh burst length RBL in a background refresh. Specifically, by dividing the size in a horizontal direction SIZE by the number of clocks MEMREF, the possible number of refresh cycles can be obtained. This division is performed by a bit shift circuit SFT. Then, the refresh burst length RBL is outputted by the address terminals A[7:4] to the memory device as 0 through 15 or 1 through 16, as shown in, for example,
Also, the active bank number generating section 1612 has an adder ADD, a third comparator CMP3, a decoder DEC0, a selector SEL0, and a decoder DEC1. The decoder DEC1 converts an input signal to an output signal with reference to a table. The active bank number generating section 1612 obtains a bank address corresponding to an access area, on the basis of the size signal.SIZE and image address ADR supplied from the image processing device. This bank address BA[1:0] indicates a bank number to be outputted along with an active command.
In the memory map shown in
ADR[9]=POSY[3], ADR[3]=POSX[3]=0, 0 BA[1:0]=0, 0 (bank BA0)
ADR[9]=POSY[3], ADR[3]=POSX[3]=0, 1 BA[1:0]=0, 1 (bank BA1)
ADR[9]=POSY[3], ADR[3]=POSX[3]=1, 0 BA[1:0]=1, 0 (bank BA2)
ADR[9]=POSY[3], ADR[3]=POSX[3]=1, 1 BA[1:0]=1, 1 (bank BA3)
Also, in a memory map that is different from the one shown in
Specifically, the decoder DEC0 outputs the outputs “0” through “7” with respect to the four combinations of ADR[9]=POSY[3], ADR[3]=POSX[3] for the case in which SIZE+ADR[2:0] exceeds or does not exceed 8. As described above, the four combinations of ADR[9]=POSY[3], ADR[3]=POSX[3] are associated with bank addresses in which the front pixels of an access area are positioned. Also, in the case in which SIZE+ADR[2:0] does not exceed 8, only one bank may be active, and in the case in which [SIZE+ADR[2:0]] exceeds 8, two banks have to be activated.
The active bank number generating section 1612 shown in
In the case of an active bankBA0 (setvalue 000b), refresh banks are BA2&3 (MAP1) or BA1&3 (Map2) in two-bank refresh, and the refresh bank is BA2 (Map1) or BA1 (Map2) in one-bank refresh.
In the case of an active bankBA1 (set value 001b), the refresh banks are BA2&3 (MAPL) or BA0&2 (Map2) in two-bank refresh, and the refresh bank is BA3 (Map1) or BA0 (Map2) in one-bank refresh.
In the case of an active bankBA2 (set value 010b), the refresh banks are BA0&1 (MAPL) or BA1&3 (Map2) in two-bank refresh, and the refresh bank is BA0 (Map1) or BA3 (Map2) in one-bank refresh.
In the case of an activebankBA3 (set value 011b), the refresh banks are BA0&1 (MAPL) or BA0&2 (Map2) in two-bank refresh, and the refresh bank is BA1 (Map1) or BA2 (Map2) in one-bank refresh.
In the case of active banks BA0&1 (set value 100b), the refresh banks are BA2&3 (MAP1) in two-bank refresh, and the refresh bank is BA2 or 3 (Map1) in one-bank refresh. The memory map Map 2 is not applicable.
In the case of active banks BA0&2 (set value 101b), the refresh banks are BA1&3 (MAP2) in two-bank refresh, and the refresh bank is BA1 or 3 (Map2) in one-bank refresh. The memory map Map 1 is not applicable.
In the case of active banks BA2&3 (set value 110b), the refresh banks are BA0-&1 (MAPL) in two-bank refresh, and the refresh bank is BA0 or 1 (Map1) in one-bank refresh. The memory map Map 2 is not applicable.
In the case of active banks BA1&3 (set value 111b), the refresh banks are BA0&2 (MAP2) in two-bank refresh, and the refresh bank is BA0 or 2 (Map2) in one-bank refresh. The memory map Map 1 is not applicable.
By defining the set values into the register 543 as described above, it is possible to arbitrarily set a memory mapping to be adopted in the system, the active bank number ACT_BA[1:0] corresponding to the eight cases of the outputs 0 through 7 of the decoder DEC0 in accordance with whether a refresh is a two-bank refresh or one-bank refresh, and the background refresh bank number BR_BA[1:0], BR_A[3:0].
The background refresh bank number generating section 1613 shown in
As described above, there are only four types of combinations of the refresh target banks with respect to the active banks in a normal access operation. Therefore, the inputs of the selector SEL1 are limited to four, but any of the four inputs of the selector SEL1 is selected in accordance with the lower two bits of the three-bit output value of the selector SEL0, whereby the refresh banks corresponding to the active banks can be generated.
Returning to
The controller 1615 supplies selection signals S2, S3, S4 corresponding to commands BREN, ACT to selectors SEL 2, 3, 4 respectively, when outputting the commands to a command CMD in response to the background refresh enable signal BR_EN. In the case in which the background refresh enable signal BR_EN is in the H level, the controller 1615 causes the selector SEL2 to selects refresh burst length RBL A[7:4], causes the selector SEL3 to select a background refresh bank number BR_BA[1:0], and causes the selector SEL4 to select a background refresh address BR_A[3:0], when outputting the command BREN. As a result, the refresh burst length RBL is outputted from the address terminal A[7:4], and the background refresh bank number BR_BA[1:0] is outputted from the bank address terminal BA[1:0]. The controller 1615 then causes the selector SEL2 to select other A[7:4], causes the selector SEL3 to select an active bank number ACT_BA[1:0], and causes the selector SEL4 to select other A[3:0], when outputting the command ACT. As a result, a normal address A[7:4] is outputted from the address terminal A[7:4], and an active target selection bank address BA[1:0] is outputted from the bank address terminal BA[1:0].
On the other hand, the memory controller 82 determines, based on the image address ADR=0x000, size signal SIZE=32, and access type signal ATYP=000b, that a horizontal access is made to the position of a front pixel of image data, POSX, POSY=0, 0, active bank ACT_BA=BA0, BA1, row address RA0, A1, and column address CA0, and that a background refresh is performed on banks BR_BA=BA2, BA3 when the refresh burst length RBL=4. The memory controller 82 then outputs a background refresh command BREN, refresh banks BA 2, 3, and refresh burst length RBL=4 at a clock number 6, further outputs an active command ACT, bank address BA0, and row address RA0 at a clock number 8, outputs an active command ACT, bank address BA1, and row address RA1 at a clock number 10, subsequently outputs a read command RD, bank address BA0, and column address CA0, then outputs a read command RD, bank address BA1, and column address CA0, and outputs a pre-charge command PER, bank address BA0, pre-charge command PER, and bank address BA1. The burst length BL of each read command is 8. Therefore, the memory controller further outputs two pairs of the above-mentioned commands ACT, RD, PRE. As a result, 32 bytes of data d0 through d31 are received from the data terminals DQ of the memory device. Then, the memory controller outputs the data d0 through d31 to the image processing device from the clock number 22 in 32-clock cycles.
The memory controller 82 outputs the appropriate refresh block count RBC to the memory along with the register set command EMRS, and sets the refresh block count RBC and the register set command EMRS into the register of the memory. In this case, the memory controller 82 determines the refresh burst length RBL from the number of clock cycles required in data transfer, in view of the refresh block count RBC, the data being obtained from the size signal SIZE. Moreover, the memory controller 82 outputs the refresh burst length RBL to the memory along with the register set command EMRS, and sets the refresh burst length RBL and the register set command EMRS into the register within the memory.
<<Method of Inputting Parameters>>The above has described the function for various accesses and refreshes performed on the memory device that stores two-dimensionally arrayed data such as image data. In this case, parameters that are required for realizing various functions are inputted from the memory controller to the memory device. The method of inputting these parameters is described hereinafter.
Moreover, in the memory device, since the column address CA4 of the adjacent page area is calculated from the column address CA7 of the access area 1740, the step number data CST of the column address within the page area is set to 4 in the register in advance.
As described above, the memory device needs to input required parameters in order to realize various accesses. As the method of inputting these parameters, there is a method of using a special input terminal, and a method of using an unused address input terminal. Furthermore, the method of inputting the parameters varies according to whether the memory device is constituted by a single data rate or double data rate SDRAM. The method of inputting the parameters also varies according to whether the address is subjected to multiple input (multiplex system) or non-multiple input (non-multiplex system) These matters are descried hereinafter.
Here, in accordance with an enable signal 1794, which indicates whether the functions are enabled disabled, if the functions are enabled, the inputted parameters are set in the mode register 1791, and if the functions are disabled, the default values are set into the mode register 1791 as the parameters. Moreover, the input buffer 1790 introduces signals from the special input terminal SP if the functions are enabled, but the enable signal 1794 is clamped to the H level if the functions are disabled. Therefore, in the case of the disabled functions, it is not necessary to connect the special input terminal SP and the input buffer 1790 by means of a bonding wire.
A two-bit start byte SB is inputted from a special input terminal SP0, then introduced to an input buffer 1790-0, and set into a mode register 1791-0. Setting into the mode register 1791-0 is performed in response to a mode register set pulse MRSPZ. However, in the case in which an enabled signal 1800 is disabled, the mode register 1791-0 is set to a default value (SB=0, start byte=0), and the output of the input buffer 1790-0 is clamped. This enable signal 1800 is supplied from a mode register MRS, bonding option, fuse circuit and the like, which are not shown.
Similarly, two-bit multi-bank information SA′ then inputted from a special input terminal SP1, and introduced into an input buffer 1790-1, and is set into a mode register 1791-1. Setting into the mode register 1791-1 is performed in response to the mode register set pulse MRSPZ. In the case in which the enable signal 1800 is disabled, the value of the mode register is set to a default value in the same manner described above (SA′=0, only one bank is selected), and the output of the input buffer is clamped.
Similarly, two-bit refresh bank information SA is inputted from a special input terminal SP2, and set into a mode register 179102. Further, in the case in which an enable signal 1802 is disabled, the value of the mode register is set to a default value in the same manner described above (SA=3, all banks are selected), and the output of the input buffer is clamped. The two-bit information items SB, SA′ are inputted from two special terminals in parallel, respectively. Alternatively, these information items may be inputted serially from one special terminal.
First, when a mode register set command MRS is inputted along with the bank addresses BA0=0, BA1=0, burst lengths that are inputted from the address terminals A0 through A2 and read latencies that are inputted from the address terminals A3 through A5 are set into the mode register 1810 at the clock rising edge RiseEdge, while write recovery values that are inputted from the address terminals A0 through A2 are set at the falling edge FallEdge.
Next, when the mode register set command MRS is inputted along with the bank addresses BA0=1, BA1=0, values (not shown) that are inputted from the address terminals A0 through A5 are set into the mode register 1811 at the clock rising edge RiseEdge, and a byte shift function flag BS, second information BMR of the byte combination information, multi-bank function flag MB, a background refresh function flag BR, and memory mapping information AR that are inputted from the address terminals A0 through A4 are set at the falling edge FallEdge. It should be noted that there are shown only the information items that indicate whether the signals are enabled or disabled. However, as described above, information that indicates the byte shift information SB, multi-bank information SA′, refresh bank information SA, refresh block count RBC or the like can also be set.
Furthermore, when the mode register set command MRS is inputted along with the bank addresses BA1=0, BA1=1, the row address step information RS that is inputted from the address terminals A0 through A5 is set into the mode register 1812 at the clock rising edge RiseEdge, and the row address step information RS that is inputted from the address terminals A0 through A5 is set at the falling edge FallEdge.
It should be noted that the mode register areas are used when test setting is performed when the bank addresses are BA0=1, BA1=1. A table 1813 shows a normal mode register MRS and an extended mode register EMRS that correspond to the combinations of the bank addresses BA0, BA1. Moreover, tables 1814 through 1819 each shows the values of the address terminals A0 through A6 in the mode register area 1811, and the set values thereof.
Next, there is described a method of inputting the parameters from unused address terminals without using the special terminals.
In the ADQ multiplex, row and column addresses are inputted at once along with the command, and thereafter the data is inputted/outputted, without inputting the active command and the write command in a time-division manner as in an SDRAM. Therefore, when the command and the address are inputted, the parameters can be inputted from unused data terminals DQ.
Also, at the CAS cycle in which the read or write command RD/WR is inputted, the 8-bit column address CA is inputted from the address terminals Add[7:0] in synchronization with the clock rising edge, and the parameter SP is inputted from any of the address terminals Add[7:0] in synchronization with the clock falling edge. This parameter SP is, for example, the start byte SB, column address step information CST, access rectangle size information (W, H), bite combination second information BMR (UP, DOWN, ALL, EVEN, ODD), or the like.
In the case of DDR and address multiplex system, there are a total of four input timings, thus unused address terminals can be used to input the parameters.
First of all, at the RAS cycle in which an active command ACT is inputted, an 8-bit row address RA is inputted from the address terminals Add[5:0] and Add[7:6] in synchronization with the clock rising edge, a 6-bit row address RA is inputted from the address terminals Add[5:0] in synchronization with the clock falling edge, and the parameter SP is inputted from the address terminals Add[7:6]. This parameter SP is, for example, the multi-bank information SA′, row address step information RS, memory map information AR, or the like.
Also, at the CAS cycle in which a read or write command RD/WR is inputted, an 8-bit column address CA is inputted from the address terminals Add[5:0] and Add[7:6] in synchronization with the clock rising edge, and the parameter SP is inputted from any of the address terminals Add[5:0], Add[7:6] in synchronization with the clock falling edge. This parameter SP is, for example, the start byte SB, column address step information CST, access rectangle size information (W, H), bits combination second information BMR (UP, DOWN, ALL, EVEN, ODD), or the like.
As described above, the parameters that are required for realizing the special functions for byte boundary access, multi-bank access and background refresh can be inputted from the special terminals or unused address terminals. The method of inputting the optimum parameters is selected, the method corresponding to the input system of the memory device.
According to the present invention, the memory cores are caused to execute the refresh operation a number of times corresponding to a plurality of refresh counts, which is set in the refresh target bank, thus the normal memory operation can be started on the refresh target bank within a short time after the background refresh operation is ended, and the decrease of the effective bandwidth can be prevented.
According to the present invention, during the normal memory operation executed by the other memory bank, the memory cores are caused to execute the refresh operation a number of times corresponding to a plurality of refresh counts, which is set in the set refresh target bank, thus the refresh operation and the normal memory operation can be executed in parallel, and the decrease of the effective bandwidth in the normal memory operation, which is caused by the refresh operation, can be prevented. Moreover, the number of times of the background refresh operation performed during the normal memory operation is set beforehand, thus the normal memory operation can be started in the refresh target bank within a short time after the background refresh operation is ended, and the decrease of the effective bandwidth can be prevented.
Further, since the memory device repeats an ordinary memory operation at a specific bank during the horizontal access period, the memory device performs the ordinary memory operation at the selected bank, and performs the refresh operation at a refresh target bank other than the horizontal access target bank. On the other hand, since it can not be predictable which bank will be a memory access target bank during the rectangular access period, it is prohibited to perform the refresh operation together with the ordinary memory operation. The horizontal access can be continued during the back ground refresh operation, accordingly, so that the effective bandwidth can be larger.
Claims
1. A memory device, comprising:
- a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and
- a control circuit, which, in response to a background refresh command and refresh burst length information, causes the memory cores within refresh target banks to successively execute refresh operation a number of times corresponding to the refresh burst length information.
2. A memory device which is operated in response to a command from a memory controller, the memory device comprising:
- a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and
- a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, while the memory cores within the refresh target banks is executing the refresh operation, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command.
3. The memory device according to claim 2, further comprising a refresh address counter which counts refresh target addresses within each of the plurality of banks or within each of a plurality of groups of the plurality of banks, wherein
- the control circuit has:
- a background refresh controller which outputs refresh control signals to the set refresh target banks in response to the background refresh command;
- a refresh burst length register in which the refresh burst length is set; and
- a core controller which is provided in each of the plurality of banks, and, in response to the background refresh control signals, causes the memory cores to execute refresh operation on the addresses of the refresh address counter a number of times corresponding to the refresh burst length set in the refresh burst length register.
4. The memory device according to claim 2, wherein
- a refresh block count which indicates the number of memory blocks activated simultaneously in a single refresh cycle is supplied, and
- the control circuit causes the refresh target banks to execute the refresh operation a number of times corresponding to the set refresh burst length, in response to the background refresh command, the refresh operation being performed for simultaneously activating the memory blocks for the number of the refresh block count.
5. The memory device according to claim 3, wherein the background refresh command and the refresh burst length are inputted simultaneously, the refresh burst length register is provided in each of the banks, and the inputted refresh burst length is set into the refresh burst length register within the refresh target bank.
6. The memory device according to claim 4, further comprising a refresh block count register, wherein
- the background refresh command and the refresh block count are inputted simultaneously, and
- the inputted refresh block count is set into the refresh block count register.
7. The memory device according to claim 3, wherein
- the refresh burst length register is provided within a mode register,
- a mode register set command and the refresh burst length are inputted simultaneously, and
- the inputted refresh burst length is set into the refresh burst length register provided within the mode register.
8. The memory device according to claim 4, wherein
- the refresh block count register is provided within a mode register,
- a mode register set command and the refresh block count are inputted simultaneously, and
- the inputted refresh block count is set into the refresh block count register provided within the mode register.
9. The memory device according to claim 3, wherein during the refresh operation executed a number of times corresponding to the refresh burst length, the core controller causes, in response to a newly inputted background refresh command, the memory cores within the refresh target banks to successively execute the refresh operation a number of times that is obtained by adding the refresh burst length to the remaining number of times of the refresh operation.
10. The memory device according to claim 3, wherein during the refresh operation executed a number of times corresponding to the refresh burst length, the core controller causes, in response to a newly inputted background refresh command, the memory cores within the refresh target banks to successively execute the refresh operation a number of times corresponding to the refresh burst length, regardless of the remaining number of times of the refresh operation.
11. The memory device according to claim 3, wherein the core controller causes, in response to a refresh-all command, the memory cores within the refresh target banks to repeatedly execute the refresh operation from the address of the refresh address counter for the remaining addresses.
12. The memory device according to claim 3, wherein during the refresh operation performed a number of times corresponding to the refresh burst length, the core controller causes the memory cores within the refresh target banks to stop the refresh operation, in response to a background refresh stop command.
13. The memory device according to claim 12, wherein, in response to the background refresh stop command, the core controller does not start a subsequent refresh operation after causing the memory cores within the refresh target banks to end the refresh operation that is being executed.
14. The memory device according to claim 3, wherein, on the basis of setting of an active refresh interlock flag in the mode register, the background refresh controller supplies the background refresh control signals to banks other than an access target bank corresponding to a bank address to be inputted, in response to a normal memory operation command.
15. The memory device according to claim 3, wherein
- the core controller has a refresh-burst length counter for count up in every refresh operation, and
- the core controller resets the refresh burst length counter in response to the background refresh command, and causes the memory cores within the refresh target banks to execute the refresh operation until a counter value of the refresh burst length counter reaches the refresh burst length that is set in the refresh burst length register.
16. The memory device according to claim 3, wherein
- the core controller has a refresh burst length counter for counted down in every refresh operation, and
- the core controller sets the refresh burst length into the refresh burst length counter in response to the background refresh command, and causes the memory cores within the refresh target banks to execute the refresh operation until a counter value of the refresh burst length counter reaches zero.
17. A memory device which is operated in response to a command sent from a memory controller, the memory device comprising:
- a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and
- a control circuit which controls operation of the memory cell arrays within the banks, wherein
- each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of which a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and
- during a period of horizontal access in which the two-dimensionally arrayed data is accessed horizontally, the control circuit causes the memory cores within banks selected by the bank addresses to execute normal memory operation corresponding to a normal operation command in response to the normal operation command corresponding to the horizontal access, and further causes a memory core within a refresh target bank other than the horizontal access target bank to execute refresh operation in response to a background refresh command.
18. The memory device according to claim 17, wherein, during a period of rectangular access in which an arbitrary rectangular area of the two-dimensionally arrayed data is accessed, the control circuit causes the memory cores within the banks selected by the bank addresses and within banks adjacent to the selected banks, to execute the normal memory operation in response to the normal operation command, and prohibits the refresh operation during the normal memory operation.
19. A memory system, comprising:
- a memory controller; and
- a memory device which is operated in response to a command from the memory controller, wherein
- the memory device has:
- a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and
- a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, during the refresh operation executed by the memory cores within the refresh target banks, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command.
20. A memory controller which controls a memory device having: a plurality of banks that respectively have memory cores including memory cell arrays and are selected by bank addresses; and a control circuit which controls operation of the memory cores within the plurality of banks,
- the memory controller comprising:
- a sequencer which, in response to an access request from a host device, supplies a normal operation command corresponding to the access request and the bank addresses to the memory device, and causes the memory cores within normal access target banks selected by the bank addresses to execute normal operation,
- the sequencer, in response to the access request, supplying, to the memory device, refresh bank information specifying banks other than the normal access target banks, and refresh burst length designating the number of times that refresh operation is performed, along with a background refresh command, and, during the normal operation, causing the memory cores within refresh target banks related to the refresh bank information to successively execute the refresh operation a number of times corresponding to the refresh burst length.
21. The memory controller according to claim 20, wherein the sequencer determines whether the background refresh command can be issued or not, on the basis of information indicating an access target data area in response to the access request, and, if the background refresh command can be issued, obtains the refresh bank information and the refresh burst length on the basis of the information indicating an access target data area.
22. The memory controller according to claim 21, further comprising a register in which are set memory map information for associating two-dimensionally arrayed data with a memory space, and bank number information for executing the refresh operation corresponding to the background refresh command, wherein
- the sequencer obtains the refresh bank information and the refresh burst length on the basis of the information indicating an access target data area and the set information of the register.
23. A memory system, comprising:
- a memory controller; and
- a memory device which is operated in response to a command from the memory controller, wherein
- the memory device has a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses,
- each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of which a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and
- the memory device further has a control circuit which causes the memory cores within banks selected by the bank addresses to execute normal memory operation corresponding to a normal operation command in response to the normal operation command during a period of horizontal access in which the two-dimensionally arrayed data is accessed horizontally, and further causes a memory core within a refresh target bank other than the horizontal access target bank to execute refresh operation in response to a background refresh command.
24. The memory system according to claim 23, wherein, during a period of rectangular access in which an arbitrary rectangular area of the two-dimensionally arrayed data is accessed, the control circuit causes the memory cores within the banks selected by the bank addresses and within banks adjacent to the selected banks, to execute the normal memory operation in response to the normal operation command, and prohibits the refresh operation during the normal memory operation.
25. A memory controller which controls a memory device having: a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and a control circuit which controls operation of the memory cores within the plurality of banks, wherein
- each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of whose a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and
- the memory controller has a sequencer which, in response to an access request from a host device, determines that the access request is for horizontal access in which the two-dimensionally arrayed data is accessed in a horizontal direction, supplies a normal operation command corresponding to the horizontal access and the bank addresses to the memory device, and causes the memory cores within horizontal access target banks selected by the bank addresses to execute normal operation,
- the sequencer, in response to the access request, supplying refresh bank information for specifying banks other than the horizontal access target banks, and a background refresh command to the memory device, and, during the normal operation, causing the memory cores within refresh target banks related to the refresh bank information to execute the refresh operation.
26. The memory controller according to claim 25, wherein when the access request is for rectangular access in which an arbitrary rectangular area of the two-dimensionally arrayed data is accessed, the sequencer supplies a normal operation command corresponding to the rectangular access and the bank addresses to the memory device, and causes the memory cores within access target banks selected by the bank addresses to execute normal operation, but does not issue the background refresh command during the normal memory operation.
Type: Application
Filed: Feb 23, 2007
Publication Date: Jun 26, 2008
Inventors: Tomohiro Kawakubo (Kawasaki), Syusaku Yamaguchi (Kawasaki), Hitoshi Ikeda (Kawasaki), Toshiya Uchida (Kawasaki), Hiroyuki Kobayashi (Kawasaki), Tatsuya Kanda (Kawasaki), Yoshinobu Yamamoto (Kawasaki), Satoru Shirakawa (Kawasaki), Tetsuo Miyamoto (Kawasaki), Tatsushi Otsuka (Kawasaki), Hidenaga Takahashi (Kawasaki), Masanori Kurita (Kawasaki), Shinnosuke Kamata (Kawasaki), Ayako Sato (Kawasaki)
Application Number: 11/709,867