Abstract: Provided is a radio communication apparatus using a battery as a power supply, in which standby electricity is reduced to achieve a reduction in power consumption. The radio communication apparatus includes a time measuring unit (210) and a plurality of time signal outputting units (220 to 22n) such that a plurality of circuit blocks are intermittently operated for a minimum period of time, only a necessary circuit block is intermittently operated, or an intermittent operation is performed with a minimum power supplied, at desired independent time intervals or after desired independent elapsed time.

Abstract: A semiconductor integrated circuit device has an electrically rewritable non-volatile memory that operates with a first power supply, and a second circuit that operates with a second power supply having a voltage lower than the voltage of the first power supply. The second circuit has a gate oxide film which is thinner than the gate oxide file of the electrically rewritable non-volatile memory. A depletion NMOS transistor has a gate connected to the second power supply, a gate oxide film whose thickness is the same as that of the gate oxide film of the electrically rewritable non-volatile memory, and transmits a signal from an output terminal of the electrically rewritable non-volatile memory to an input terminal of the second circuit.

Abstract: Provided is a radio communication apparatus using a battery as a power supply, in which standby electricity is reduced to achieve a reduction in power consumption. The radio communication apparatus includes a time measuring unit (210) and a plurality of time signal outputting units (220 to 22n) such that a plurality of circuit blocks are intermittently operated for a minimum period of time, only a necessary circuit block is intermittently operated, or an intermittent operation is performed with a minimum power supplied, at desired independent time intervals or after desired independent elapsed time.

Abstract: Provided is a semiconductor integrated circuit device including a reset signal generating circuit for detecting a plurality of power source voltages in which a consumption current is low and a circuit area is small. The semiconductor integrated circuit device includes the reset signal generating circuit. The reset signal generating circuit includes a plurality of voltage detecting circuits whose consumption currents are not changed even when a power source voltage significantly changes, in which output signal terminals of the voltage detecting circuits are connected with gate electrodes of a plurality of N-channel enhancement MIS transistors connected in series with an output node of a current mirror circuit to simultaneously perform an amplification and a logical operation on output signals of the voltage detecting circuits, to thereby realize low power consumption even in a wide operating voltage range and with a reduced circuit area.

Abstract: In an integrated circuit having two circuits operating at different power supply voltages a level shifter, which transmits a signal from a high voltage operation circuit to a low voltage operation circuit, is composed of a depletion NMOS transistor with its gate electrode fixed to the potential of the power supply voltage of the low voltage operation circuit.

Abstract: A latch circuit is configured so that even if a power-on-reset circuit is not operated in putting a power supply to work, a depletion type MIS transistor is connected as a pull-down element to an output terminal of an RS latch to thereby reliably activate the RS latch in a reset state, whereby a circuit or a semiconductor integrated circuit device is prevented from being unintendedly operated. Furthermore, channel impurities of the depletion type MIS transistor are introduced into only a part, whereby it is possible to realize a semiconductor integrated circuit device which is excellent in safety and which is readily operated with less current consumption and with low cost.

Abstract: A MOS semiconductor device is manufactured by providing a gate electrode on a semiconductor substrate through a silicon oxide film and disposing a resist mask pattern in contact with the silicon oxide film. The resist mask pattern has a fully opened region and a partially opened region disposed between the fully opened region and the gate electrode. The partially opened region has alternating masked portions and portions exposing the silicon oxide film which partly block and partly permit, respectively, the introduction of impurities therethrough. Impurities are selectively introduced into an impurity introduction region of the semiconductor substrate through the fully opened region and the partially opened region of the resist mask pattern to form areas having high and low impurity densities in the impurity introduction region.

Abstract: There is provided a voltage detecting circuit in which a consumed electric current is small, accuracy is high, and an erroneous operation seldom occurs. In the voltage detecting circuit constituted by a bias circuit, a current mirror circuit, a load MIS transistor connected to the current mirror circuit in which current drive capability is changed by an output voltage of the bias circuit, and an amplifying inverter circuit, a potential change at an output node of the current mirror circuit at the time of detection and release of a power supply voltage is steeply changed, so that a leak current of the whole circuit can be decreased and a consumed electric current can be reduced.

Abstract: A latch circuit is arranged by means for detecting a signal, a unit for holding a signal detection condition, and a unit for releasing the signal detection condition. When a detection output produced from the detecting unit is entered into the signal detection condition holding unit, the signal detection condition holding unit continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto. The signal detection condition releasing unit produces a release signal only when the power supply is turned ON. Once the signal detection condition holding unit holds the signal detection condition, the signal detection condition holding unit is reset to an undetection condition only when the power supply is interrupted and then is again turned ON. The latch circuit can firmly reset the stopped system to the initial condition by merely again turning ON the power supply.

Abstract: A latch circuit is configured so that even if a power-on-reset circuit is not operated in putting a power supply to work, a depletion type MIS transistor is connected as a pull-down element to an output terminal of an RS latch to thereby reliably activate the RS latch in a reset state, whereby a circuit or a semiconductor integrated circuit device is prevented from being unintendedly operated. Furthermore, channel impurities of the depletion type MIS transistor are introduced into only a part, whereby it is possible to realize a semiconductor integrated circuit device which is excellent in safety and which is readily operated with less current consumption and with low cost.

Abstract: A latch circuit is arranged by means for detecting a signal, a unit for holding a signal detection condition, and a unit for releasing the signal detection condition. When a detection output produced from the detecting unit is entered into the signal detection condition holding unit, the signal detection condition holding unit continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto. The signal detection condition releasing unit produces a release signal only when the power supply is turned ON. Once the signal detection condition holding unit holds the signal detection condition, the signal detection condition holding unit is reset to an undetection condition only when the power supply is interrupted and then is again turned ON. The latch circuit can firmly reset the stopped system to the initial condition by merely again turning ON the power supply.

Abstract: A latch circuit is arranged by means for detecting a signal, a unit for holding a signal detection condition, and a unit for releasing the signal detection condition. When a detection output produced from the detecting unit is entered into the signal detection condition holding unit, the signal detection condition holding unit continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto. The signal detection condition releasing unit produces a release signal only when the power supply is turned ON. Once the signal detection condition holding unit holds the signal detection condition, the signal detection condition holding unit is reset to an undetection condition only when the power supply is interrupted and then is again turned ON. The latch circuit can firmly reset the stopped system to the initial condition by merely again turning ON the power supply.

Abstract: There is provided a voltage detecting circuit in which a consumed electric current is small, accuracy is high, and an erroneous operation seldom occurs. In the voltage detecting circuit constituted by a bias circuit, a current mirror circuit, a load MIS transistor connected to the current mirror circuit in which current drive capability is changed by an output voltage of the bias circuit, and an amplifying inverter circuit, a potential change at an output node of the current mirror circuit at the time of detection and release of a power supply voltage is steeply changed, so that a leak current of the whole circuit can be decreased and a consumed electric current can be reduced.

Abstract: A non-volatile memory circuit has FLOTOX type memory elements operable with a low data writing voltage even when a difference between threshold voltages of non-volatile memory elements is small. Each data bit is held by two non-volatile memory elements for storing data having a complementary logic relationship. Potentials at data lines are supplied to inputs of a sense amplifier so that even a small potential difference can be detected. As a result, data stored in a pair of non-volatile FLOTOX type memory elements having shallow data writing depths can be read.

Abstract: A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.

Abstract: In an FLOTOX type non-volatile memory circuit, while a data writing voltage is low, even when a difference between a threshold voltage of a non-volatile memory element under enhancement state and a threshold voltage thereof under depletion state is small, the data can be surely read out from the non-volatile memory element in a high speed. Also, a total data rewritable time can be increased. In the non-volatile memory circuit, since 1-bit data is held by using two sets of non-volatile memory elements capable of storing thereinto data having a complementary relationship with each other, even when a difference between threshold voltages of these two non-volatile memory elements is small, the data can be surely read thereof. When data is read by using a differential type sense amplifier, potentials at a Data line and a DataX line are entered to two inputs of this sense amplifier, so that even such a small potential difference can be detected.

Abstract: A method of manufacturing a semiconductor device comprises providing on a semiconductor substrate a mask pattern having a fully opened region and a partially opened region. Impurities are selectively introduced into an impurity introduction region of the semiconductor substrate through the fully opened region and the partially opened region of the mask pattern to form areas having high and low impurity densities in the impurity introduction region.

Abstract: A memory circuit is provided which is capable of writing data with a simplified configuration and hence being improved in usability. The present invention comprises a fuse 10 having one end to which a bias voltage Vcc is to be applied from an internal power supply to have a disconnect/connect state storing data 0/1, a thyristor 11 having an anode terminal connected to the internal power supply through the fuse 10 and a cathode terminal being ground, an N-channel MOS transistor 12 having a drain terminal connected to a gate terminal of the thyristor 11 and a source terminal being ground, and a read-out circuit 14 for reading out data 0/1 stored on the fuse 10 through the N-channel MOS transistor 13.

Abstract: In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region 104 having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region 105 having a second impurity concentration determined by doping an impurity to the region selected by a pattern 106 of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region 104 having the first impurity concentration and the channel region 105 having the second impurity concentration are divided into a plurality of plane shapes.

Abstract: An low-power consumption integrated ring oscillator capable of stable operation throughout a wide voltage range without undergoing a large frequency change includes a first constant voltage generating circuit having an enhancement mode P-MOS transistor and a depletion mode N-MOS transistor and a second constant voltage generating circuit having a depletion mode N-MOS transistor and an enhancement mode N-MOS transistor. A first constant voltage generated by the first constant voltage circuit is applied to a gate electrode of a P-MOS transistor of transmission gates connected between respective cascaded inverters of the ring oscillator. A second constant voltage generated by the second constant voltage generating circuit is connected to the gate electrode of an N-MOS transistor of the transmission gates. By this construction, current consumption is reduced and battery lifetime can be increased. The boosting circuit for writing and erasing an EEPROM circuit may be formed with the low power ring oscillator.