Patents by Inventor Masanori Takeuchi

Masanori Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120281168
    Abstract: Each picture element includes first and second sub-picture elements, each of which includes a liquid crystal capacitor and at least one storage capacitor. After a display voltage representing a certain grayscale level has been applied to the respective sub-picture element electrodes of the first and second sub-picture elements, a voltage difference ?V? is produced between voltages to be applied to the respective liquid crystal capacitors of the first and second sub-picture elements by way of their associated storage capacitor(s). By setting the voltage difference ?V? value of the blue and/or cyan picture element(s) to be smaller than that of the other color picture elements, shift toward the yellow range at an oblique viewing angle can be minimized.
    Type: Application
    Filed: July 17, 2012
    Publication date: November 8, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Fumikazu SHIMOSHIKIRYOH, Kentaroh IRIE, Masanori TAKEUCHI, Nobuyoshi NAGASHIMA, Toshihide TSUBATA
  • Patent number: 8304769
    Abstract: An active matrix substrate of the present invention is arranged so that each pixel area has a transistor and a capacity electrode which is able to function as an electrode of a capacity. The active matrix substrate includes a conductor which is provided in a layer below the capacity electrode and is able to function as the other electrode of the capacity. The gate electrode of each transistor and a gate insulating film covering the conductor have a thin section with reduced thickness, in an on-conductor area overlapping the conductor. At least a part of the thin section overlaps the capacity electrode. In this way, the active matrix substrate which can reduce inconsistency in capacitance values of capacities (e.g. a storage capacitor, a capacity for controlling an electric potential of a pixel electrode, and a capacity which can function as both of them) provided in the substrate.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: November 6, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihide Tsubata, Masanori Takeuchi
  • Publication number: 20120236226
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Application
    Filed: September 12, 2011
    Publication date: September 20, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki NODA, Toshihide TSUBATA, Masanori TAKEUCHI, Kenji ENDA
  • Publication number: 20120194573
    Abstract: In the liquid crystal display device (100) of this invention, pixels include m kinds of (where m is an even number and m?4) pixels (R, G, B and Y) that display different colors. The pixels are arranged so that n of the m kinds of pixels (where n is an even number, n?m and n is a divisor of m) are repeatedly arranged in the same order in the row direction. Each row of pixels formed by those pixels includes groups of pixels, to each of which n pixels arranged consecutively in the row direction belong. Grayscale voltages of opposite polarities are applied through associated signal lines (13) to the pixel electrodes (11) of two arbitrary adjacent pixels in each group of pixels. In two arbitrary groups of pixels that are adjacent in the row direction, grayscale voltages of opposite polarities are applied through their associated signal lines to the pixel electrodes of pixels that display the same color.
    Type: Application
    Filed: August 27, 2010
    Publication date: August 2, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuki Yamashita, Akihiro Shohraku, Masanori Takeuchi
  • Patent number: 8193649
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: June 5, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
  • Patent number: 8168980
    Abstract: In an active matrix substrate of the present invention, a gate insulating film for covering a gate electrode of each transistor has a thin portion, having a reduced film thickness, which is provided on a part overlapped on the gate electrode, and the thin portion is formed by using the gate electrode, on which the thin portion is overlapped, as a mask, and each transistor has a first drain electrode section and a second drain electrode section which are respectively provided on both sides of a source electrode, and the thin portion has two edges opposite to each other, and the first drain electrode section is overlapped on the one edge, and the second drain electrode section is overlapped on the other edge. This makes it possible to provide an active matrix substrate which realizes high display quality while suppressing unevenness of parasitic capacitances (particularly, Cgd) of TFTs in the active matrix substrate whose each TFT has a thin portion in its gate insulating film.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: May 1, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihide Tsubata, Masanori Takeuchi
  • Patent number: 8170106
    Abstract: Apparatus including: a unit detecting a motion vector, among plural number of fields included in motion pictures, or fields, produced from the plural number of fields; a unit for converting the motion pictures into light-emission data for sub-fields; a unit for reconstructing the light-emission data for sub-fields, via calculating using the motion vector; and a unit for displaying the picture using the light-emission data outputted from the sub-field reconstruction unit, wherein the sub-field reconstruction unit selects the motion vector ending at a reconstruction target pixel of other one (1) field, among the motion vectors detected by the motion vector detection unit, and calculates a position vector, by multiplying a predetermined function onto this, and thereby reconstructing light-emission data for one (1) sub-field of the reconstruction target pixel, using the light-emission data for sub-fields corresponding to the one (1) sub-fields within the pixel, which is indicated by the position vector.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: May 1, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hideharu Hattori, Koichi Hamada, Yasuhiro Akiyama, Masanori Takeuchi
  • Patent number: 8130172
    Abstract: A display method of a plasma display device and plasma display device are provided. The display method includes nonlinearly converting first image data corresponding to an input image signal to second image data having a gradation value smaller than a gradation value of first image data and expressing the second image data by a real part and an error part. The display method includes error diffusing of, when the error part of the second image data is not zero, spatially or temporally diffusing the error part. The display method includes subfield pattern converting of selecting a lighting pattern of the subfields based on the error-diffused second image data.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 6, 2012
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Masanori Takeuchi, Akira Yamamoto
  • Patent number: 8089571
    Abstract: An active matrix substrate (12) includes a substrate, a TFT (24) formed on the substrate, a storage capacitor element (20) formed on the substrate, an interlayer insulating film covering the storage capacitor element (20), and a pixel electrode (21) formed on the interlayer insulating film. The storage capacitor element (20) includes a storage capacitor line (27), an insulating film formed on the storage capacitor line (27), and two or more storage capacitor electrodes (25a, 25b, 25c) opposed to the storage capacitor line (27) with the insulating film interposed therebetween. The two or more storage capacitor electrodes (25a, 25b, 25c) are electrically connected via associated contact holes (26a, 26b, 26c) formed in the interlayer insulating film to the pixel electrode (21) and electrically continuous with a drain electrode of the TFT (24).
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: January 3, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshifumi Yagi, Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Patent number: 8089573
    Abstract: A liquid crystal panel (10) includes an active matrix substrate on which a transistor (12), a pixel electrode (17), signal lines (15, 16) and backup wirings (8a, 8b) for recovering a defect in the signal line are formed; a color filter substrate on which a common electrode (counter electrode) is formed; and a liquid crystal material provided between the active matrix substrate and the color filter substrate. The backup wirings (8a, 8b) are (electrically) connected to the common electrode on the color filter substrate, through (i) a protection circuit (9) for discharging an undesired electric charge that occurs in the backup wirings (8a, 8b) and (ii) a sealing adhesive (6). With this configuration, it becomes possible to reduce problems (for instance, unexpected short-circuiting of the backup wiring and the signal line) caused by the undesired electric charge that occurs in the backup wirings.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: January 3, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Matsuda, Masanori Takeuchi
  • Publication number: 20110279764
    Abstract: An active matrix substrate has a structure that prevents a drain extraction line from breaking without a plurality of active elements such as thin film transistor elements, metal-insulator-metal elements, MOS transistor elements, diodes, and varistors being disposed, and is suited for use in a large-size liquid crystal television or a like liquid crystal display device equipped with a large-size liquid crystal display panel. The active matrix substrate includes an active element connected, via a drain extraction line, to a storage capacitor upper electrode, wherein the drain extraction line has at least two routes.
    Type: Application
    Filed: August 1, 2011
    Publication date: November 17, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Ryuji KURIHARA, Yuhko HISADA, Toshihide TSUBATA, Masanori TAKEUCHI, Tomokazu OHTSUBO
  • Publication number: 20110267569
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki NODA, Masanori TAKEUCHI, Kenji ENDA
  • Patent number: 8035768
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: October 11, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Patent number: 8031282
    Abstract: An active matrix substrate has a structure that prevents a drain extraction line from breaking without a plurality of active elements such as thin film transistor elements, metal-insulator-metal elements, MOS transistor elements, diodes, and varistors being disposed, and is suited for use in a large-size liquid crystal television or a like liquid crystal display device equipped with a large-size liquid crystal display panel. The active matrix substrate includes an active element connected, via a drain extraction line, to a storage capacitor upper electrode, wherein the drain extraction line has at least two routes.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: October 4, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ryuji Kurihara, Yuhko Hisada, Toshihide Tsubata, Masanori Takeuchi, Tomokazu Ohtsubo
  • Patent number: 8022559
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: September 20, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
  • Patent number: 8023056
    Abstract: An active matrix substrate including, in each pixel area, a transistor, a pixel electrode (17), a conductive member (18) functioning as one of electrodes of a storage capacitor, a drain lead-out (7) electrode connected to a drain electrode of the transistor, and overlapping with the conductive member (18), and a contact hole for connecting the drain lead-out electrode (7) to the pixel electrode (17), includes a gate insulating film (40) covering a gate electrode of each transistor, the gate insulating film including a first thickness portion (41) overlapping with at least part of the contact hole, and a second thickness portion (42) formed adjacent to the first thickness portion, and overlapping with the drain lead-out electrode, the first thickness portion (41) having a greater thickness than the second thickness portion (42).
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: September 20, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masanori Takeuchi, Toshihide Tsubata
  • Patent number: 8008789
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 30, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
  • Publication number: 20110205500
    Abstract: Transmission-type screens are placed corresponding to a display board at a front area of the display board, on which an article is placed. Each of the screens transmits and projects a projector image luminous flux projected from a backside of the screens to a front side of the screens. When the projector image luminous flux is projected from the backside of the screens, each of inner circumferences which defines a space including an image projecting space for leading the projector image luminous flux to the backside of the screens without obstruction. A display shelf might have a projector and a computer. The projector projects the projector image luminous flux. The display shelf might have a reflecting mirror which lead the projector image flux to the screens.
    Type: Application
    Filed: May 3, 2011
    Publication date: August 25, 2011
    Applicant: Toshiba Tec Kabushiki Kaisha
    Inventors: Yoshihiko Ikeda, Hiroki Mochizuki, Masanori Takeuchi, Makoto Nozawa, Yun Wang
  • Patent number: 8004476
    Abstract: A technique capable of suppressing or preventing generation of flickers (blinks) by a sustain period control as well as capable of ensuring or enhancing display quality in a PDP device. The PDP device adjusts a sustain pulse of the sustain period for every subfield by selecting a combination of one or more than one cycle so that start and end timings of a field in fields before and after change are almost the same according to a display load ratio of the subfield of the field. Field weighted emission center positions then becomes almost the same, and flickers and the like are suppressed.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: August 23, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takeuchi, Toshio Ueda
  • Patent number: 7978273
    Abstract: An active-matrix substrate includes: scanning signal lines; data signal lines; first storage capacitor wires; second storage capacitor wires; and pixels, disposed at intersections between the scanning signal lines and the data signal lines, each of which includes a plurality of sub-pixels. Each of the data signal lines is split into two parts at a region where the number of scanning signal lines intersecting the data signal line is ½ of the total number of scanning signal lines. A data signal line split section is formed on a region that does not overlap the second storage capacitor wires. This makes it possible to provide an active-matrix substrate, a display device, and a television receiver in each of which a data signal line split into two parts and a storage capacitor wire are hardly electrically short-circuited in the case of a combination of a split-screen structure and a multi-pixel structure.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: July 12, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masanori Takeuchi, Toshihide Tsubata