Abstract: A failbit counting method includes controlling a counter of a verify failbit count (VFC) circuit to count fail bits in a bit group including one or more verification bits, received at an input of the counter, to obtain a count result in unary format. Each of the one or more verification bits is a fail bit or a pass bit. The count result in unary format is stored in the counter. The method further includes controlling the counter to transcode the count result stored in the counter from unary format to binary format.

Abstract: The present disclosure provides memories, operation methods of memories, and memory systems. An example memory includes: a memory cell array, word lines, a first select line, and a peripheral circuit. The peripheral circuit is configured to: in a first period of a recovery period of a verify operation, apply a first voltage to a first word line, and apply a second voltage to a second word line, wherein the second voltage is greater than the first voltage; in a second period of the recovery period of the verify operation, apply a third voltage to the first select line; and in a third period of the recovery period of the verify operation, apply a fourth voltage to the first word line, and apply a fifth voltage to the second word line, wherein the fifth voltage is greater than the fourth voltage.

Abstract: A page buffer circuit of a memory device includes a first sensing branch including a first pre-charge path and a low-voltage latch, and a second sensing branch including a second pre-charge path and a sensing latch. The first sensing branch and the second sensing branch are parallel coupled to a sensing node of the page buffer circuit.

Abstract: A memory device includes a memory cell array including memory planes and a peripheral circuit coupled to the memory cell array. The peripheral circuit includes selected voltage selection circuits, global word line voltage selection circuits coupled to the selected voltage selection circuits, and local word line voltage selection circuits coupled to the global word line voltage selection circuits. Each memory plane corresponds to the plurality of selected voltage selection circuits. Each memory plane corresponds to respective global word line voltage selection circuits of the global word line voltage selection circuits. Each memory plane corresponds to respective local word line voltage selection circuits of the local word line voltage selection circuits. At least one of the selected voltage selection circuits is configured to apply a program voltage and a read voltage.

Abstract: The present disclosure provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes; a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane. The plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits.

Abstract: A verify failbit count (VFC) circuit includes a counter including a plurality of counter stages coupled one after another and including one or more cache stages in a cache group and a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages. Each of the reception stages is configured to receive one of a plurality of verification bits generated by a verification operation of a memory device. The counter further includes one or more switches each coupled between two neighboring ones of the plurality of reception groups.

Abstract: A failbit counting method includes controlling a counter of a verify failbit count (VFC) circuit to count fail bits in a bit group including one or more verification bits, received at an input of the counter, to obtain a count result in unary format. Each of the one or more verification bits is a fail bit or a pass bit. The count result in unary format is stored in the counter. The method further includes controlling the counter to transcode the count result stored in the counter from unary format to binary format.

Abstract: A verify failbit count (VFC) circuit includes a counter circuit and a transcoder circuit. The counter circuit includes a counter. The counter is configured to count one or more fail bits based on results of a verification operation of a memory device to obtain a count result in unary format. The transcoder circuit includes a transcoder coupled to the counter. The transcoder is configured to transcode the count result in unary format to a transcoded result in binary format.

Abstract: A failbit counting method includes sequentially receiving, at an input of a counter, a bit group including one or more verification bits. Each of the one or more verification bits is a fail bit or a pass bit. The counter includes one or more counter stages coupled in series from the input. The method further includes, for one verification bit of the one or more verification bits, performing a determination process according to a position of the one verification bit in the group to select one of the one or more counter stages for writing a fail bit or to decide to discard the one verification bit.

Abstract: Aspects of the present disclosure provide a memory, a control method thereof, and a memory system. The memory includes a memory cell array and a peripheral circuit, the peripheral circuit comprising at least a trigger circuit comprising a reference signal output circuit and a fail bit signal output circuit, wherein the fail bit signal output circuit is configured to generate a fail bit signal according to a test signal obtained from verification of the memory, and the reference signal output circuit is configured to output a plurality of reference signals; and a comparator coupled with the trigger circuit and configured to compare the fail bit signal with the at least one reference signal to output a verification result.

Abstract: A page buffer circuit of a memory device includes a first sensing branch including a first pre-charge path and a low-voltage latch, and a second sensing branch including a second pre-charge path and a sensing latch. The first sensing branch and the second sensing branch are parallel coupled to a sensing node of the page buffer circuit.

Abstract: The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment of a bit line, and a second bit line segment sensing branch connected to a second bit line segment of the bit line. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit. In some embodiments, the first bit line segment sensing branch comprises a first sense latch and a first bit line pre-charge path, and the second bit line segment sensing branch comprises a second sense latch and a second bit line pre-charge path.

Abstract: The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.

Abstract: The present disclosure provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes; a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane. The plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits.

Abstract: A semiconductor device includes a bit line unit, a word line unit, a bit line drive unit, and a word line drive unit. The bit line unit is configured to divide the word line unit into a first word line unit and a second word line unit. The distance between the second word line unit and the word line drive unit is greater than that the distance between the first word line unit and the word line drive unit. The word line drive unit is configured to provide the driving voltage for programming to the word line unit. The bit line drive unit is configured to apply the first bias voltage to the bit line unit that performs the dividing to obtain the first word line unit in the charging phase of programming, and to apply the second bias voltage to the bit line unit that performs the dividing to obtain the second word line unit in the discharging phase of programming.

Abstract: The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.

Abstract: The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment of a bit line, and a second bit line segment sensing branch connected to a second bit line segment of the bit line. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit. In some embodiments, the first bit line segment sensing branch comprises a first sense latch and a first bit line pre-charge path, and the second bit line segment sensing branch comprises a second sense latch and a second bit line pre-charge path.

Abstract: An error check and correction method employs a circuit which includes a data storage unit configured to store a data string; a syndrome calculation unit configured to calculate a syndrome from the data string; an error coefficient calculation unit configured to calculate coefficients of an error location search equation using the syndrome; a latch unit configured to store the coefficients; a substitution value calculation unit configured to calculate a substitution value using the coefficients stored in the latch unit and an address; a Chien search unit configured to output an error detection signal indicating for each bit of the data string whether an error exists, in response to a result obtained by substituting the substitution value in the error location search equation; and an error correction unit configured to correct the error in response to the error detection signal indicating that the error exists.

Abstract: An error check and correction method employs a circuit which includes a data storage unit configured to store a data string; a syndrome calculation unit configured to calculate a syndrome from the data string; an error coefficient calculation unit configured to calculate coefficients of an error location search equation using the syndrome; a latch unit configured to store the coefficients; a substitution value calculation unit configured to calculate a substitution value using the coefficients stored in the latch unit and an address; a Chien search unit configured to output an error detection signal indicating for each bit of the data string whether an error exists, in response to a result obtained by substituting the substitution value in the error location search equation; and an error correction unit configured to correct the error in response to the error detection signal indicating that the error exists.

Abstract: Integrated circuit memory devices include multiple voltage regulators configured to generate respective boosted voltages, which are provided to a memory cell block. A first voltage regulator is configured to increase a well voltage (Vwell) from a first level to an elevated second level during a pull-up time interval when a boosted well voltage level is required within a memory cell block. The increase in the level of the well voltage occurs in response to a transition of a trim signal (Trim) received at an input of the first voltage regulator. A second voltage regulator is also provided. The second voltage regulator is configured to increase a word line voltage (Vwl) from a third level to an elevated fourth level during the pull-up time interval, in response to the transition of the trim signal and in response to the well voltage. A memory cell block is provided, which is configured to receive the well voltage and the word line voltage during the pull-up time interval.