Patents by Inventor Masao Kuriyama

Masao Kuriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8990667
    Abstract: An error check and correction method employs a circuit which includes a data storage unit configured to store a data string; a syndrome calculation unit configured to calculate a syndrome from the data string; an error coefficient calculation unit configured to calculate coefficients of an error location search equation using the syndrome; a latch unit configured to store the coefficients; a substitution value calculation unit configured to calculate a substitution value using the coefficients stored in the latch unit and an address; a Chien search unit configured to output an error detection signal indicating for each bit of the data string whether an error exists, in response to a result obtained by substituting the substitution value in the error location search equation; and an error correction unit configured to correct the error in response to the error detection signal indicating that the error exists.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Masao Kuriyama
  • Publication number: 20140040699
    Abstract: An error check and correction method employs a circuit which includes a data storage unit configured to store a data string; a syndrome calculation unit configured to calculate a syndrome from the data string; an error coefficient calculation unit configured to calculate coefficients of an error location search equation using the syndrome; a latch unit configured to store the coefficients; a substitution value calculation unit configured to calculate a substitution value using the coefficients stored in the latch unit and an address; a Chien search unit configured to output an error detection signal indicating for each bit of the data string whether an error exists, in response to a result obtained by substituting the substitution value in the error location search equation; and an error correction unit configured to correct the error in response to the error detection signal indicating that the error exists.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 6, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: MASAO KURIYAMA
  • Patent number: 8493795
    Abstract: Integrated circuit memory devices include multiple voltage regulators configured to generate respective boosted voltages, which are provided to a memory cell block. A first voltage regulator is configured to increase a well voltage (Vwell) from a first level to an elevated second level during a pull-up time interval when a boosted well voltage level is required within a memory cell block. The increase in the level of the well voltage occurs in response to a transition of a trim signal (Trim) received at an input of the first voltage regulator. A second voltage regulator is also provided. The second voltage regulator is configured to increase a word line voltage (Vwl) from a third level to an elevated fourth level during the pull-up time interval, in response to the transition of the trim signal and in response to the well voltage. A memory cell block is provided, which is configured to receive the well voltage and the word line voltage during the pull-up time interval.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Masao Kuriyama
  • Publication number: 20110157976
    Abstract: Integrated circuit memory devices include multiple voltage regulators configured to generate respective boosted voltages, which are provided to a memory cell block. A first voltage regulator is configured to increase a well voltage (Vwell) from a first level to an elevated second level during a pull-up time interval when a boosted well voltage level is required within a memory cell block. The increase in the level of the well voltage occurs in response to a transition of a trim signal (Trim) received at an input of the first voltage regulator. A second voltage regulator is also provided. The second voltage regulator is configured to increase a word line voltage (Vwl) from a third level to an elevated fourth level during the pull-up time interval, in response to the transition of the trim signal and in response to the well voltage. A memory cell block is provided, which is configured to receive the well voltage and the word line voltage during the pull-up time interval.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 30, 2011
    Inventor: Masao Kuriyama
  • Patent number: 7952953
    Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a first memory block including a first memory cell; a second memory block including a second memory cell; and a column decoder circuit accessing the first memory cell of the first memory block through a first conductor line and accessing the second memory cell of the second memory block through a second conductor line, wherein the column decoder circuit activates the first and second conductor lines in response to one of an address for reading the first memory cell and an address for reading the second memory cell.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Masao Kuriyama
  • Patent number: 7848160
    Abstract: A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Masao Kuriyama
  • Patent number: 7738299
    Abstract: According to an example embodiment, an erase discharge method may include drawing charges accumulated in a floating gate of a floating gate type field effect transistor into a semiconductor substrate to perform an erase operation by applying a first voltage to a word line, a second voltage to an N-well and a P-well, and/or opening a bit line and a ground line. The word line may be grounded, and a discharge transistor connected to the bit line may be turned on. The N-well and the P-well may be grounded to discharge charges accumulated in the N-well and P-well.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Masao Kuriyama, Makoto Hirano, Hiroki Murakami, Yuichiro Nakagaki
  • Patent number: 7714637
    Abstract: A negative potential discharge circuit may include an internal voltage generating circuit and/or a discharge unit. The internal voltage generating circuit may be configured to generate a regulated output voltage based on a power supply voltage. The discharge unit may be configured to discharge a negative potential using the regulated output voltage. A method of discharging a negative potential may include generating a regulated output voltage based on a power supply voltage, and/or discharging a negative potential using the regulated output voltage.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Masao Kuriyama
  • Patent number: 7605643
    Abstract: A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Masao Kuriyama
  • Publication number: 20090201749
    Abstract: A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.
    Type: Application
    Filed: December 12, 2008
    Publication date: August 13, 2009
    Inventor: Masao Kuriyama
  • Publication number: 20090180347
    Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a first memory block including a first memory cell; a second memory block including a second memory cell; and a column decoder circuit accessing the first memory cell of the first memory block through a first conductor line and accessing the second memory cell of the second memory block through a second conductor line, wherein the column decoder circuit activates the first and second conductor lines in response to one of an address for reading the first memory cell and an address for reading the second memory cell.
    Type: Application
    Filed: December 16, 2008
    Publication date: July 16, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Masao KURIYAMA
  • Patent number: 7420863
    Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: September 2, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Honda, Masao Kuriyama
  • Patent number: 7414892
    Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: August 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Honda, Masao Kuriyama
  • Patent number: 7397716
    Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: July 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Honda, Masao Kuriyama
  • Publication number: 20080123434
    Abstract: According to an example embodiment, an erase discharge method may include drawing charges accumulated in a floating gate of a floating gate type field effect transistor into a semiconductor substrate to perform an erase operation by applying a first voltage to a word line, a second voltage to an N-well and a P-well, and/or opening a bit line and a ground line. The word line may be grounded, and a discharge transistor connected to the bit line may be turned on. The N-well and the P-well may be grounded to discharge charges accumulated in the N-well and P-well.
    Type: Application
    Filed: June 26, 2007
    Publication date: May 29, 2008
    Inventors: Masao Kuriyama, Makoto Hirano, Hiroki Murakami, Yuichiro Nakagaki
  • Patent number: 7345919
    Abstract: A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: March 18, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Honda, Hideo Kato, Hidetoshi Saito, Masao Kuriyama, Tokumasa Hara, Takafumi Ikeda, Tatsuya Hiramatsu
  • Publication number: 20070297242
    Abstract: A negative potential discharge circuit may include an internal voltage generating circuit and/or a discharge unit. The internal voltage generating circuit may be configured to generate a regulated output voltage based on a power supply voltage. The discharge unit may be configured to discharge a negative potential using the regulated output voltage. A method of discharging a negative potential may include generating a regulated output voltage based on a power supply voltage, and/or discharging a negative potential using the regulated output voltage.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 27, 2007
    Inventor: Masao Kuriyama
  • Publication number: 20070296487
    Abstract: A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 27, 2007
    Inventor: Masao Kuriyama
  • Publication number: 20070242517
    Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
    Type: Application
    Filed: June 15, 2007
    Publication date: October 18, 2007
    Inventors: Yasuhiko HONDA, Masao Kuriyama
  • Publication number: 20070236998
    Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
    Type: Application
    Filed: June 15, 2007
    Publication date: October 11, 2007
    Inventors: Yasuhiko Honda, Masao Kuriyama