Patents by Inventor Masao Kuriyama
Masao Kuriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935619Abstract: The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.Type: GrantFiled: March 4, 2022Date of Patent: March 19, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Teng Chen, Yan Wang, Masao Kuriyama
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Publication number: 20240029793Abstract: The present disclosure provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes; a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane. The plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits.Type: ApplicationFiled: October 26, 2022Publication date: January 25, 2024Inventors: Zhihong Li, Jing Wei, Masao Kuriyama
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Publication number: 20240005993Abstract: A semiconductor device includes a bit line unit, a word line unit, a bit line drive unit, and a word line drive unit. The bit line unit is configured to divide the word line unit into a first word line unit and a second word line unit. The distance between the second word line unit and the word line drive unit is greater than that the distance between the first word line unit and the word line drive unit. The word line drive unit is configured to provide the driving voltage for programming to the word line unit. The bit line drive unit is configured to apply the first bias voltage to the bit line unit that performs the dividing to obtain the first word line unit in the charging phase of programming, and to apply the second bias voltage to the bit line unit that performs the dividing to obtain the second word line unit in the discharging phase of programming.Type: ApplicationFiled: December 29, 2022Publication date: January 4, 2024Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yan WANG, Chunyuan HOU, Masao KURIYAMA, Zhichao DU, Lichuan ZHAO
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Publication number: 20220415370Abstract: The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment of a bit line, and a second bit line segment sensing branch connected to a second bit line segment of the bit line. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit. In some embodiments, the first bit line segment sensing branch comprises a first sense latch and a first bit line pre-charge path, and the second bit line segment sensing branch comprises a second sense latch and a second bit line pre-charge path.Type: ApplicationFiled: March 4, 2022Publication date: December 29, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Teng CHEN, Yan WANG, Masao KURIYAMA
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Publication number: 20220415372Abstract: The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.Type: ApplicationFiled: March 4, 2022Publication date: December 29, 2022Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Teng CHEN, Yan Wang, Masao Kuriyama
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Patent number: 8990667Abstract: An error check and correction method employs a circuit which includes a data storage unit configured to store a data string; a syndrome calculation unit configured to calculate a syndrome from the data string; an error coefficient calculation unit configured to calculate coefficients of an error location search equation using the syndrome; a latch unit configured to store the coefficients; a substitution value calculation unit configured to calculate a substitution value using the coefficients stored in the latch unit and an address; a Chien search unit configured to output an error detection signal indicating for each bit of the data string whether an error exists, in response to a result obtained by substituting the substitution value in the error location search equation; and an error correction unit configured to correct the error in response to the error detection signal indicating that the error exists.Type: GrantFiled: August 2, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Masao Kuriyama
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Publication number: 20140040699Abstract: An error check and correction method employs a circuit which includes a data storage unit configured to store a data string; a syndrome calculation unit configured to calculate a syndrome from the data string; an error coefficient calculation unit configured to calculate coefficients of an error location search equation using the syndrome; a latch unit configured to store the coefficients; a substitution value calculation unit configured to calculate a substitution value using the coefficients stored in the latch unit and an address; a Chien search unit configured to output an error detection signal indicating for each bit of the data string whether an error exists, in response to a result obtained by substituting the substitution value in the error location search equation; and an error correction unit configured to correct the error in response to the error detection signal indicating that the error exists.Type: ApplicationFiled: August 2, 2013Publication date: February 6, 2014Applicant: Samsung Electronics Co., Ltd.Inventor: MASAO KURIYAMA
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Patent number: 8493795Abstract: Integrated circuit memory devices include multiple voltage regulators configured to generate respective boosted voltages, which are provided to a memory cell block. A first voltage regulator is configured to increase a well voltage (Vwell) from a first level to an elevated second level during a pull-up time interval when a boosted well voltage level is required within a memory cell block. The increase in the level of the well voltage occurs in response to a transition of a trim signal (Trim) received at an input of the first voltage regulator. A second voltage regulator is also provided. The second voltage regulator is configured to increase a word line voltage (Vwl) from a third level to an elevated fourth level during the pull-up time interval, in response to the transition of the trim signal and in response to the well voltage. A memory cell block is provided, which is configured to receive the well voltage and the word line voltage during the pull-up time interval.Type: GrantFiled: December 17, 2010Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Masao Kuriyama
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Publication number: 20110157976Abstract: Integrated circuit memory devices include multiple voltage regulators configured to generate respective boosted voltages, which are provided to a memory cell block. A first voltage regulator is configured to increase a well voltage (Vwell) from a first level to an elevated second level during a pull-up time interval when a boosted well voltage level is required within a memory cell block. The increase in the level of the well voltage occurs in response to a transition of a trim signal (Trim) received at an input of the first voltage regulator. A second voltage regulator is also provided. The second voltage regulator is configured to increase a word line voltage (Vwl) from a third level to an elevated fourth level during the pull-up time interval, in response to the transition of the trim signal and in response to the well voltage. A memory cell block is provided, which is configured to receive the well voltage and the word line voltage during the pull-up time interval.Type: ApplicationFiled: December 17, 2010Publication date: June 30, 2011Inventor: Masao Kuriyama
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Patent number: 7952953Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a first memory block including a first memory cell; a second memory block including a second memory cell; and a column decoder circuit accessing the first memory cell of the first memory block through a first conductor line and accessing the second memory cell of the second memory block through a second conductor line, wherein the column decoder circuit activates the first and second conductor lines in response to one of an address for reading the first memory cell and an address for reading the second memory cell.Type: GrantFiled: December 16, 2008Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Masao Kuriyama
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Patent number: 7848160Abstract: A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.Type: GrantFiled: December 12, 2008Date of Patent: December 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Masao Kuriyama
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Patent number: 7738299Abstract: According to an example embodiment, an erase discharge method may include drawing charges accumulated in a floating gate of a floating gate type field effect transistor into a semiconductor substrate to perform an erase operation by applying a first voltage to a word line, a second voltage to an N-well and a P-well, and/or opening a bit line and a ground line. The word line may be grounded, and a discharge transistor connected to the bit line may be turned on. The N-well and the P-well may be grounded to discharge charges accumulated in the N-well and P-well.Type: GrantFiled: June 26, 2007Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Masao Kuriyama, Makoto Hirano, Hiroki Murakami, Yuichiro Nakagaki
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Patent number: 7714637Abstract: A negative potential discharge circuit may include an internal voltage generating circuit and/or a discharge unit. The internal voltage generating circuit may be configured to generate a regulated output voltage based on a power supply voltage. The discharge unit may be configured to discharge a negative potential using the regulated output voltage. A method of discharging a negative potential may include generating a regulated output voltage based on a power supply voltage, and/or discharging a negative potential using the regulated output voltage.Type: GrantFiled: June 22, 2007Date of Patent: May 11, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Masao Kuriyama
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Patent number: 7605643Abstract: A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.Type: GrantFiled: June 21, 2007Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Masao Kuriyama
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Publication number: 20090201749Abstract: A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.Type: ApplicationFiled: December 12, 2008Publication date: August 13, 2009Inventor: Masao Kuriyama
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Publication number: 20090180347Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a first memory block including a first memory cell; a second memory block including a second memory cell; and a column decoder circuit accessing the first memory cell of the first memory block through a first conductor line and accessing the second memory cell of the second memory block through a second conductor line, wherein the column decoder circuit activates the first and second conductor lines in response to one of an address for reading the first memory cell and an address for reading the second memory cell.Type: ApplicationFiled: December 16, 2008Publication date: July 16, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Masao KURIYAMA
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Patent number: 7420863Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.Type: GrantFiled: June 15, 2007Date of Patent: September 2, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Honda, Masao Kuriyama
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Patent number: 7414892Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.Type: GrantFiled: June 15, 2007Date of Patent: August 19, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Honda, Masao Kuriyama
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Patent number: 7397716Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.Type: GrantFiled: April 11, 2006Date of Patent: July 8, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Honda, Masao Kuriyama
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Publication number: 20080123434Abstract: According to an example embodiment, an erase discharge method may include drawing charges accumulated in a floating gate of a floating gate type field effect transistor into a semiconductor substrate to perform an erase operation by applying a first voltage to a word line, a second voltage to an N-well and a P-well, and/or opening a bit line and a ground line. The word line may be grounded, and a discharge transistor connected to the bit line may be turned on. The N-well and the P-well may be grounded to discharge charges accumulated in the N-well and P-well.Type: ApplicationFiled: June 26, 2007Publication date: May 29, 2008Inventors: Masao Kuriyama, Makoto Hirano, Hiroki Murakami, Yuichiro Nakagaki