Abstract: Redundant cell arrays 201 of a plurality of columns are provided for replacing a defective bit line of a memory cell array 101. Each of the redundant cell arrays 201 is provided with a redundant sense amplifier circuit 105 separately from a sense amplifier circuit 103 of the memory cell array 101. A defective address storing circuit 108 stores a defective address of the memory cell array 101, an input/output terminal, to and from which data corresponding to the defective address are. to be inputted and outputted, and a column set number of the redundant cell array which is to be replaced in accordance with the input/output terminal. An address comparator circuit 109 detects the coincidence of an input address with the defective address. A switch circuit 112 is controlled by the coincidence detection output to switch one corresponding to the defective address of a sense amplifier circuit to one selected by the set number in the redundant sense amplifier circuit, to connect it to a data input/output buffer 113.

Abstract: A first and a second transistor are connected to an output node. A first and a second differential amplifier compare a reference voltage with the voltage supplied from a voltage setting circuit. When the voltage at the output node is raised, the differential amplifier drives the first transistor, thereby charging the output node. In addition, when the voltage at the output node is lowered, the second differential amplifier drives the second transistor, thereby discharging the charges at the output node. The voltage setting circuit connected to the output node is composed of a current-summing D/A converter. In the voltage setting circuit, the value of the load resistance is varied according to the voltage appearing at the output node.

Abstract: In a non-volatile semiconductor memory device, a binary counter is connected to a most significant bit portion of an address counter for successively generating addresses of rows of a memory cell array. The binary counter forcibly selects one of spare row lines, and permits a pre-program operation (program operation prior to data erasure) to be performed on memory cells connected to the selected one of spare row lines, when the pre-program operation has completely been performed on the memory cells of the rows of the memory cell array. In the pre-program operation, whether or not to verify data is determined on the basis of a coincidence signal outputted from a defective row address storing section.

Abstract: A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.

Abstract: A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines.

Abstract: Each of first and second cell array groups has a cell array and a row decoder. Circuit blocks including a reset transistor, a Y selector, a write transistor, a block decoder, and a source decoder except the cell array and row decoder are arranged in the area between the first and second cell array groups. Since an address signal, a control signal, and a power supply common to the circuit blocks can be shared, the layout area can be reduced.

Abstract: A nonvolatile semiconductor memory system is provided with a nonvolatile memory cell array divided into erase blocks data and refresh blocks, and a flag cell array including a plurality of nonvolatile flag cells each of which corresponds to one of the refresh blocks and stores data representing the refresh status of the corresponding refresh block.

Abstract: A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines.

Abstract: In a non-volatile semiconductor memory device, a binary counter is connected to a most significant bit portion of an address counter for successively generating addresses of rows of a memory cell array. The binary counter forcibly selects one of spare row lines, and permits a pre-program operation (program operation prior to data erasure) to be performed on memory cells connected to the selected one of spare row lines, when the pre-program operation has completely been performed on the memory cells of the rows of the memory cell array. In the pre-program operation, whether or not to verify data is determined on the basis of a coincidence signal outputted from a defective row address storing section.

Abstract: Each of first and second cell array groups has a cell array and a row decoder. Circuit blocks including a reset transistor, a Y selector, a write transistor, a block decoder, and a source decoder except the cell array and row decoder are arranged in the area between the first and second cell array groups. Since an address signal, a control signal, and a power supply common to the circuit blocks can be shared, the layout area can be reduced.

Abstract: A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.

Abstract: The total number of bits of irregular blocks is equal to the number of bits of one equal block. The memory cells of the irregular blocks are sequentially designated using an address counter used to designate the memory cells of equal blocks. An erase operation (including pre program and erase operations) starts from "verify". Only when "verify" is NG, the pre program and erase operations are performed. A means capable of fixing a verify result VERIOK at "1" (verify OK) is arranged to always set VERIOK at "1" for a non-select block of the irregular blocks, thereby preventing execution of the pre program and erase operations for the non-select block of the irregular blocks. Accordingly, in the boot block type, the same address counter is shared by the equal and irregular blocks to reduce the circuit scale.

Abstract: A memory cell array has a plurality of memory cells formed of EEPROM cells arranged in a matrix form. Data in the memory cells is flash-erased, and after this, word lines other than a selected word line are set to a negative potential and erasing verification for detecting an insufficiently erased memory cell is effected. The flash-erasing and erasing verification are repeatedly effected until no insufficiently erased memory cell is detected. When no insufficiently erased memory cell is detected, word lines other than a selected word line are set to a negative potential and an overerased memory cell is detected. When an overerased memory cell is detected, weak program is effected for the cell by applying a voltage lower than the normal writing voltage to the cell.

Abstract: In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.

Abstract: A semiconductor integrated circuit device includes a test mode setting circuit. The test mode setting circuit includes an AND circuit for deriving the logical AND of a test mode setting permission signal and a signal input from a pin, and a latch circuit which is set by an output of the AND circuit and reset by a test mode setting release signal. After the test content is latched in the latch circuit in response to a test mode setting permission signal, the test is effected according to the setting of state of the semiconductor integrated circuit device and data latched in the latch circuit.

Abstract: A bias voltage generating circuit supplies a bias voltage to a memory's bit lines. One end of a first transistor is connected to a first power supply. The first transistor conducts in response to a control signal. A second transistor is connected to another end of the first transistor. Another end of the second transistor and a gate of the second transistor are connected to an output node. One end of a third transistor and a gate connected to the output node. One end of a fourth transistor and a gate are connected to a second end of the third transistor. A second end of the fourth transistor is connected to a second power supply. One end of a fifth transistor is connected to the first power supply. The fifth transistor also conducts in response to the control signal. A sixth transistor is connected to a second end of the fifth transistor. A second end of the sixth transistor is connected to the output node and the gate of the sixth transistor is connected to a potential source.

Abstract: A data input circuit outputs input data in accordance with a write enable signal. A program control circuit generates different data items on the basis of the input data output from the data input circuit and the write enable signal, and turns programming transistors on/off in accordance with the different data items as generated. The programming transistors are connected to a pair of cell transistors forming an EPROM cells, and program into these cell transistors the different data items generated by the write control circuit. A timing circuit delays the timing at which the write enable signal is supplied to the write control circuit, until the input data is established within the data input circuit.

Abstract: An apparatus and a method are provided for employing hard monochromatic x-rays to generate high resolution, dimensionally altered undistorted images of either the internal structure or surface feature details of a specimen at the submicron level in up to three-dimensions. A monochromatic hard x-ray beam is applied to the specimen and thereafter is directed to arrive at a small angle of incidence at a preferably flat, optically polished surface of a nearly perfect crystal, to be diffracted at the surface thereof to carry a first one-dimensional alteration of the image of the observed structure of the specimen. This x-ray beam is then directed, at a small angle of incidence, to the surface of a second nearly perfect crystal, the receiving surface being oriented orthogonal to the surface of the first nearly perfect crystal, to generate a further diffracted beam containing an undistorted two-dimensionally altered inverted image of the specimen with micrometer spatial resolution.

Abstract: A process for improving the properties, particularly the dyeing properties, of cellulose fibers. The process comprises impregnating cellulose fiber with an aromatic acyl halide and thereafter immersing the impregnated fiber into an aqueous solution containing more than about 10% by weight of an alkali hydroxide to acylate the cellulose fiber on the surface portion thereof. In another embodiment of the invention, a continuous process for improving the properties of cellulose fiber yarn or fabric is provided. According to the continuous process, uniform acylation is achieved by maintaining the yarn or fabric in a stretched state during impregnation with the aromatic acyl halide and during the initial stages of immersion in the aqueous alkali hydroxide. The acylated cellulose fiber produced according to the invention may be dyed with good color fastness with disperse dyes and still retain the soft tactility characteristic of the fiber.

Abstract: A cellulose fiber derivative is provided, along with methods of its production, in order to give color features to cellulose fiber compositions while using disperse dyes. The cellulose fiber derivative includes an acyl group of formula ##STR1## wherein X.sub.1, X.sub.2, Y.sub.1, Y.sub.2 and Z are selected individually from the group consisting of hydrogen, halogen, alkyl, nitro, methoxy, phenylazo or amino, introduced into said cellulose fiber through chemical reaction with the hydroxyl groups of said cellulose fiber to the extent of a substitution degree of more than 0.10.