Patents by Inventor Masao Morimoto
Masao Morimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170358344Abstract: A multiport memory includes an address control circuit, a memory array, a data input-output circuit and a control circuit and first and second address signals and a clock signal are input through two ports. The address control circuit includes first and second latch circuits, a selection circuit, a decode circuit and a word line drive circuit. The first address signal input through one port is input into the first latch circuit and the second address signal input through the other port is input into the selection circuit. The selection circuit selects one of the first and second address signals, the second latch circuit latches and outputs the selected address signal to the decode circuit. The word line drive circuit drives a word line on the basis of an output signal from the decode circuit.Type: ApplicationFiled: April 6, 2017Publication date: December 14, 2017Inventors: Yuichiro ISHII, Makoto YABUUCHI, Masao MORIMOTO
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Publication number: 20170309327Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: July 13, 2017Publication date: October 26, 2017Inventors: Shigenobu KOMATSU, Masanao YAMAOKA, Noriaki MAEDA, Masao MORIMOTO, Yasuhisa SHIMAZAKI, Yasuyuki OKUMA, Toshiaki SANO
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Publication number: 20170306237Abstract: Provided is a composition which can be used for formation of an optical film having high quality and a high dichroic ratio even after the composition is stored for a predetermined period of time. The composition includes a compound represented by the general formula (A) and a compound represented by the general formula (B), wherein R1a in the general formula (A) and R1b in the general formula (B) are mutually different groups.Type: ApplicationFiled: April 24, 2017Publication date: October 26, 2017Inventors: Masao MORIMOTO, Noriyuki HIDA
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Publication number: 20170305930Abstract: Provided is an optical film which has a maximum absorption at a wavelength in the range of 600 to 680 nm, has a high dichroic ratio, and is excellent in light resistance. The optical film includes: a polymer of a polymerizable liquid crystal compound; and a compound represented by the following general formula (1).Type: ApplicationFiled: April 24, 2017Publication date: October 26, 2017Inventors: Masao MORIMOTO, Noriyuki HIDA
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Publication number: 20170271344Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: ApplicationFiled: June 7, 2017Publication date: September 21, 2017Inventors: Masao MORIMOTO, Noriaki MAEDA, Yasuhisa SHIMAZAKI
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Patent number: 9734893Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: February 22, 2016Date of Patent: August 15, 2017Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 9704873Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: GrantFiled: May 26, 2016Date of Patent: July 11, 2017Assignee: Renesas Electronics CorporationInventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Publication number: 20160276352Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: ApplicationFiled: May 26, 2016Publication date: September 22, 2016Inventors: Masao MORIMOTO, Noriaki MAEDA, Yasuhisa SHIMAZAKI
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Patent number: 9385133Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: GrantFiled: October 23, 2015Date of Patent: July 5, 2016Assignee: Renesas Electronics CorporationInventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Publication number: 20160172022Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Inventors: Shigenobu KOMATSU, Masanao YAMAOKA, Noriaki MAEDA, Masao MORIMOTO, Yasuhisa SHIMAZAKI, Yasuyuki OKUMA, Toshiaki SANO
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Patent number: 9368194Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: April 21, 2015Date of Patent: June 14, 2016Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Publication number: 20160043091Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Inventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Publication number: 20160016885Abstract: A method produces optically active trans-1,2-diaminocyclohexane, in which a crystal of optically active trans-1,2-diaminocyclohexane is obtained by crystallization from a solution of optically active trans-1,2-diaminocyclohexane. Optically active trans-1,2-diaminocyclohexane with high purity is obtained in a favorable yield from a solution of optically active trans-1,2-diaminocyclohexane. The optically active trans-1,2-diaminocyclohexane with high purity is useful as a raw material for a large number of medicines.Type: ApplicationFiled: March 13, 2014Publication date: January 21, 2016Applicant: Toray Fine Chemicals Co., Ltd.Inventors: Seiji MORII, Masao MORIMOTO
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Patent number: 9196622Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: GrantFiled: December 22, 2014Date of Patent: November 24, 2015Assignee: Renesas Electronics CorporationInventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Publication number: 20150228330Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: April 21, 2015Publication date: August 13, 2015Inventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 9053975Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: September 18, 2014Date of Patent: June 9, 2015Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Publication number: 20150102421Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: ApplicationFiled: December 22, 2014Publication date: April 16, 2015Inventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Patent number: 8957459Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: GrantFiled: July 26, 2012Date of Patent: February 17, 2015Assignee: Renesas Electronics CorporationInventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Publication number: 20150001633Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: September 18, 2014Publication date: January 1, 2015Inventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 8854869Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: August 12, 2010Date of Patent: October 7, 2014Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano