Patents by Inventor Masao Okihara

Masao Okihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622263
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 14, 2020
    Assignees: LAPIS SEMICONDUCTOR CO., LTD., Inter-University Research Institute Corporation High Energy Accelerator Research Organization
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Patent number: 10559607
    Abstract: A semiconductor device includes a substrate having a main surface, the main surface including a first region and a second region, and an element separation region that disposed on a boundary between the first region and the second region, a first filter disposed on the main surface in the first region, and a second filter disposed on the main surface in the second region, the first filter and the second filter overlapping each other in the element separation region in a plan view of the semiconductor device.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 11, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masao Okihara
  • Publication number: 20190360962
    Abstract: A measurement device including: an ion-sensitive element; a reference electrode disposed in a state in which a measurement subject is interposed between the reference electrode and the ion-sensitive element; and a controller configured to: establish a first state at a predetermined interval, the first state being a state in which a current flows at the ion-sensitive element, and establish a second state within each period after the first state has been established and before the first state is next established, the second state being a state in which a potential difference between the ion-sensitive element and the reference electrode is greater than a potential difference between the ion-sensitive element and the reference electrode in the first state.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 28, 2019
    Inventors: KENICHIRO KUSANO, ATSUHIKO OKADA, HIROAKI SANO, MASAO OKIHARA
  • Publication number: 20190187088
    Abstract: A reference electrode is provided with an accommodation portion that is provided with a tube-shaped lead-out portion that can guide an accommodated internal liquid; a liquid junction portion that is connected to an end of the lead-out portion, and that allows the internal liquid to seep out; a liquid dripping portion that has a first end connected to the liquid junction portion, that has a second end that protrudes into the accommodation portion, and that guides the internal liquid to the liquid junction portion; and an internal electrode having at least a portion that is positioned further towards the first end side than the second end of the liquid dripping portion.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 20, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Masao OKIHARA
  • Publication number: 20180247960
    Abstract: A semiconductor device includes a substrate having a main surface, the main surface including a first region and a second region, and an element separation region that disposed on a boundary between the first region and the second region, a first filter disposed on the main surface in the first region, and a second filter disposed on the main surface in the second region, the first filter and the second filter overlapping each other in the element separation region in a plan view of the semiconductor device.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 30, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Masao OKIHARA
  • Patent number: 9978783
    Abstract: A semiconductor device includes first and second photo-electric conversion elements, each having a light-receiving surface, disposed adjacent to each other, each outputting a light current that is a current corresponding to an intensity of received light, a first filter disposed on the light-receiving surface of the first photo-electric conversion element, a second filter disposed on the light-receiving surface of the second photo-electric conversion element, and a third filter disposed on the light-receiving surface of the second photo-electric conversion element and being in contact with the second filter, one end of the second filter and one end of the third filter overlapping one end of the first filter at a vicinity of a boundary between the first photo-electric conversion element and the second photo-electric conversion element.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 22, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masao Okihara
  • Publication number: 20180138232
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Applicants: LAPIS Semiconductor Co., Ltd., Inter-University Research Institute Corporation High Energy Accelerator Research Organization
    Inventors: Yasuo ARAI, Masao OKIHARA, Hiroki KASAI
  • Patent number: 9899448
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 20, 2018
    Assignees: LAPIS Semiconductor Co., Ltd., INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Patent number: 9876126
    Abstract: A semiconductor device that includes: a pair of photoelectric transducers that output photocurrent that accords with an intensity of received light; and a first filter film that is provided to a light incidence side of one out of the pair of photoelectric transducers, that is configured by alternatingly stacking high refractive index layers and low refractive index layers having mutually different refractive indexes, and that transmits one out of either UV-A waves or UV-B waves included in ultraviolet rays with a higher transmittance than the other out of the UV-A waves and the UV-B waves.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 23, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masao Okihara
  • Publication number: 20170338256
    Abstract: A semiconductor device includes first and second photo-electric conversion elements, each having a light-receiving surface, disposed adjacent to each other, each outputting a light current that is a current corresponding to an intensity of received light, a first filter disposed on the light-receiving surface of the first photo-electric conversion element, a second filter disposed on the light-receiving surface of the second photo-electric conversion element, and a third filter disposed on the light-receiving surface of the second photo-electric conversion element and being in contact with the second filter, one end of the second filter and one end of the third filter overlapping one end of the first filter at a vicinity of a boundary between the first photo-electric conversion element and the second photo-electric conversion element.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 23, 2017
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Masao OKIHARA
  • Publication number: 20170117421
    Abstract: A semiconductor device that includes: a pair of photoelectric transducers that output photocurrent that accords with an intensity of received light; and a first filter film that is provided to a light incidence side of one out of the pair of photoelectric transducers, that is configured by alternatingly stacking high refractive index layers and low refractive index layers having mutually different refractive indexes, and that transmits one out of either UV-A waves or UV-B waves included in ultraviolet rays with a higher transmittance than the other out of the UV-A waves and the UV-B waves.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 27, 2017
    Inventor: MASAO OKIHARA
  • Publication number: 20160190203
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Yasuo ARAI, Masao OKIHARA, Hiroki KASAI
  • Patent number: 9318391
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: April 19, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Patent number: 9136386
    Abstract: An SOI substrate includes a semiconductor base; a semiconductor layer formed over the semiconductor base; and a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically isolate the semiconductor layer from the semiconductor base, where the buried insulating film contains a nitride film.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 15, 2015
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masao Okihara
  • Publication number: 20150126002
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 7, 2015
    Inventors: Yasuo ARAI, Masao OKIHARA, Hiroki KASAI
  • Patent number: 8963246
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: February 24, 2015
    Assignees: Inter-University Research Institute Corporation High Energy Accelerator Research Organization, LAPIS Semiconductor Co., Ltd.
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Publication number: 20130043537
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Application
    Filed: March 9, 2011
    Publication date: February 21, 2013
    Applicants: LAPIS Semiconductor Co., Ltd., INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Patent number: 8362562
    Abstract: In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: January 29, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Masao Okihara
  • Publication number: 20120193714
    Abstract: Disclosed is an SOI substrate which includes a semiconductor base; a semiconductor layer formed over the semiconductor base; and a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically isolate the semiconductor layer from the semiconductor base, where the buried insulating film contains a nitride film.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 2, 2012
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: MASAO OKIHARA
  • Patent number: 8217361
    Abstract: An ultraviolet sensor has an ultraviolet detection diode having a depletion region 18 formed in an Si layer 16 on an insulating layer 14, an interlayer insulating film 20 formed on the ultraviolet detection diode, and a wiring 24 formed on the interlayer insulating film 20. An incident angle ? (°) of an incident light entering into the depletion region 18 and a film thickness Tsi (nm) of the depletion region 18 satisfy the following formula (1), which is also shown in FIG. 14.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: July 10, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masao Okihara