Abstract: A semiconductor device includes a substrate, a first oxide film lying on the substrate, a thin semiconductor film lying on the first oxide film, a first terminal formed on the semiconductor film, a second terminal formed on the semiconductor film, a semiconductor element formed on the semiconductor film and electrically connected between the first and second terminals, and a protective diode formed on the semiconductor film and electrically connected in between the second and first terminal in a forward direction.

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional, doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract: The present invention adequately activates a substrate contact region of a support substrate without substantially changing the conventional SOI-CMOS device formation process. An exposed face of the support substrate is formed in an element isolation region of a layered substrate, which includes a support substrate having a first semiconductor layer, an insulating layer provided on the support substrate, and a second semiconductor layer provided on the insulating layer, by etching away the insulating layer and the second semiconductor layer. A substrate contact region is then formed in the support substrate by performing ion implantation from the side of the exposed face of the support substrate. Thereafter, an element isolation insulation layer is formed on the exposed face of the support substrate and a gate oxide film and a gate electrode are formed on the remaining second semiconductor layer.

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract: The dependency of threshold voltage on adjusted bias voltage is varied between N-channel and P-channel MOSFETs. A support substrate, an insulating layer on the support substrate, and island-shaped first and second silicon layers separately formed on the insulating layer; a first MOSFET formed of a fully depleted SOI where a first channel part is formed in a first silicon layer; and a second MOSFET formed of a partially depleted SOI where a second channel part is formed in a second silicon layer, the second MOSFET configures a complementary MOSFET with the first MOSFET, are provided. The threshold voltage of the second MOSFET formed of the partially depleted SOI is hardly varied because of a neutral region in the second channel part, although bias voltage is applied to the support substrate to vary the threshold voltage of the first MOSFET formed of the fully depleted SOI.

Abstract: A MOSFET device including a semiconductor substrate, an SiGe layer provided on top of the semiconductor substrate, an Si layer provided on top of the SiGe layer; and a first isolation region for separating the Si layer into a first region and a second region, wherein the Si layer in the second region is turned into an Si epitaxial layer greater in thickness than the Si layer in the first region. The MOSFET device further includes at least one first MOSFET with the Si layer in the first region serving as a strained Si channel, and at least one second MOSFET with the Si epitaxial layer serving as an Si channel.

Abstract: The dependency of threshold voltage on adjusted bias voltage is varied between an N-channel MOSFET and a P-channel MOSFET. A support substrate, an insulating layer disposed on the support substrate, and island-shaped first and second silicon layers separately formed on the insulating layer; a first MOSFET formed of a fully depleted SOI where a first channel part is formed in the first silicon layer; and a second MOSFET formed of a partially depleted SOI where a second channel part is formed in the second silicon layer, the second MOSFET configures a complementary MOSFET with the first MOSFET, are provided. The threshold voltage of the second MOSFET formed of the partially depleted SOI is hardly varied because of a neutral region disposed in the second channel part, even though bias voltage is applied to the support substrate to vary the threshold voltage of the first MOSFET formed of the fully depleted SOI.

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract: A MOSFET device comprises a semiconductor substrate, an SiGe layer provided on top of the semiconductor substrate, a Si layer provided on top of the SiGe layer; and a first isolation region for separating Si layer into a first region and a second region, wherein the Si layer in the second region is turned into an Si epitaxial layer larger in thickness than the Si layer in the first region. The MOSFET device further comprises at least one first MOSFET with the Si layer in the first region serving as a strained Si channel, and at least one second MOSFET with the Si epitaxial layer serving as an Si channel.

Abstract: Described here is a method of forming a thin-film portion for allowing electrons produced from a transmission electron microscope to pass therethrough at a portion to be observed of a semiconductor and effecting a predetermined etching process on the thin-film portion thereby to create a semiconductor sample for the transmission electron microscope. Prior to the execution of the etching process, grooves for reducing a stress introduced into the thin-film portion by the etching process are defined in the thin-film portion.

Abstract: A field effect transistor and a method for forming the field effect transistor are made up of a source region which is formed on the substrate, a drain region which is formed on the substrate, a stepped portion which is formed in the substrate between the source region and the drain region, a gate insulating film which is formed on the stepped portion of the substrate, and a gate electrode which is formed on the gate insulating film, wherein, a thickness of the gate insulating film near the drain region, which is less than that of the gate insulating film on a channel region defined in the substrate between the source region and the drain region. Accordingly, the field effect transistor and a method for forming the field effect transistor can prevent degradation of transistor characteristics because of a hot carrier effect.

Abstract: A plan-view sample of an integrated circuit is prepared for transmission electron microscopy by marking a faulty circuit element, lapping the upper surface of the sample to a mirror finish, lapping the lower surface to reduce the thickness of the entire sample, and further processing the lower surface by lapping or dimpling, combined with ion milling as necessary, to thin the sample in the vicinity of the fault. A sample prepared in this way affords a wide view, and can be tilted at large angles. A known thickness of a particular type of layer in the sample can be left by holding the sample at a predetermined angle while the sample is lapped.