Abstract: There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

Abstract: A method of generating an exposure pattern for lithography to create a plurality of patterns arranged in a predetermined direction, comprises a step of counting the plurality of patterns along this predetermined direction, and generating a first enlarged pattern by moving the edges to a first direction along the predetermined direction for a pattern with an odd number, and by moving the edges to a second direction, which is opposite to the first direction, for a pattern with an even number, and a step of generating a second enlarged pattern by moving the edges to the second direction for the pattern with an odd number, and by moving the edges to the first direction for the pattern with an even number. And the first and second patterns are used for creating the plurality of original patterns in a lithography step using the respective enlarged patterns.

Abstract: An object of the present invention is to discriminate received information from one and same originator visually and readily. A CPU detects identification information of the originator in receiving a facsimile. It also selects identification information which coincides with the identification information detected among identification information of originators stored in a printing color table in a RAM in advance and selects a printing color corresponding to the identification information. A signal generating circuit generates an index signal which instructs to print an index mark in a selected printing color. The CPU controls an operation of a color printer so as to print the index mark in a predetermined color based on the index signal together with image information. It is possible to discriminate information transmitted from a predetermined terminal by selecting the recording sheet on which the index mark of the predetermined printing color is printed out of the mixed recording sheets.

Abstract: A semiconductor device having a memory cell region comprising a plurality of memory cells is described, and a stable characteristic is imparted to all the memory cells provided in the memory cell block. Impurities are implanted into a memory cell region of a silicon substrate at predetermined intervals, thus forming a plurality of wells. A resist film used as a mask for implanting impurities has strip-shaped patterns and a broad pattern. Since the strip-shaped patterns located close to the broad pattern are inclined, the characteristics of the wells located in the vicinity of the outer periphery of the memory cell region become unstable. The wells having unstable characteristics are taken as dummy wells which do not affect the function of a semiconductor device.

Abstract: Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

Abstract: While being transferred in substantially horizontal state along a predetermined path of transfer by a conveyer means, a substrate plate is dried by a jet of compressed air which is spurted out from a slit-like mouth of an air knife nozzle crosswise of the entire width of the substrate plate and at a predetermined angle of incidence with respect to a drying surface of the substrate plate to scrape off a liquid. The angle of incidence of jet air is made shallower as soon as the substrate on the conveyer means comes to a point of entry to an air blasting zone and is made deeper at latest when the substrate plate comes to a position immediately before a point of disengagement from the air blasting zone.

Abstract: A semiconductor device having a memory cell region comprising a plurality of memory cells is described, and a stable characteristic is imparted to all the memory cells provided in the memory cell block. Impurities are implanted into a memory cell region of a silicon substrate at predetermined intervals, thus forming a plurality of wells. A resist film used as a mask for implanting impurities has strip-shaped patterns and a broad pattern. Since the strip-shaped patterns located close to the broad pattern are inclined, the characteristics of the wells located in the vicinity of the outer periphery of the memory cell region become unstable. The wells having unstable characteristics are taken as dummy wells which do not affect the function of a semiconductor device.

Abstract: A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

Abstract: There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

Abstract: A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

Abstract: Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

Abstract: While being transferred in substantially horizontal state along a predetermined path of transfer by a conveyer means, a substrate plate is dried by a jet of compressed air which is spurted out from a slit-like mouth of an air knife nozzle crosswise of the entire width of the substrate plate and at a predetermined angle of incidence with respect to a drying surface of the substrate plate to scrape off a liquid. The angle of incidence of jet air is made shallower as soon as the substrate on the conveyer means comes to a point of entry to an air blasting zone and is made deeper at latest when the substrate plate comes to a position immediately before a point of disengagement from the air blasting zone.

Abstract: A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

Abstract: A method of manufacturing a semiconductor device which prevents a short circuit between a gate electrode and a diffusion layer region if a contact hole is shifted from its proper position. A material having an etch selectivity to an interlayer insulation film is formed over the gate electrode to serve as a cover against the formation of a contact hole. A material is not formed over an interconnect line which is required to be exposed to a contact hole.

Abstract: After formation of a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate. The Ti layer is then silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

Abstract: After formation a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate, and then the Ti layer is silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

Abstract: An interconnection structure of a semiconductor device with a gate electrode, an active region provided in the vicinity of the gate electrode and a first buried layer in a contact hole exposing the gate electrode and the active region. The contact hole is easily formed, and the first buried layer has a substantially low interconnection resistance value.

Abstract: An engine has first and second cylinder rows substantially parallel to each other and is mounted sideways so that the cylinder rows are arranged side by side in the longitudinal direction of the vehicle body with the first cylinder row disposed forward of the second cylinder row. An exhaust system for the engine has first and second exhaust pipes. The first exhaust pipe is connected to the cylinders in the first cylinder row on the front side of the first cylinder row and is led rearward of the engine through a recess formed on the lower side of an oil pan of the engine which is positioned between the first and second cylinder rows. The second exhaust pipe is connected to the cylinders in the second cylinder row on the rear side of the second cylinder row, is once led forward into the recess of the oil pan and then turned rearward in the recess to extend rearward. The first and second exhaust pipes are merged into a common exhaust pipe at a junction in the rear of the engine.