Abstract: A sliding bearing 5 is composed of a pair of halved bearings 11, 12 and is provided with crush reliefs 11E, 12E in positions adjoining abutment surfaces 11B, 12B of these halved bearings. Chamfered portions 11D, 12D are formed in inward edge portions of the above-described abutment surfaces 11B, 12B, and a dust pocket 15 is formed on the middle side of the chamfered portions 11D, 12D. The relative angle ? formed by the above-described crush reliefs 11E, 12E with sliding surfaces 13 in positions adjoining the crush reliefs 11E, 12E is set at 0.69° or more. Foreign substances 14 in a lubricating oil are discharged from openings of side portions of the crush reliefs 11E, 12E to the outside and are prevented from easily entering the sliding surfaces 13. A sliding bearing excellent in seizure resistance compared to that of conventional art can be provided.

Abstract: The present invention provides a photosensor that uses a phase modulation technique for optical detection and conducts a highly accurate measurement. The photosensor uses a phase change difference of light propagated through a polarization preserving fiber with respect to tensile stress and employs proper polarization preserving fibers for a phase modulator 10, light-transmitting polarization preserving fiber 23, and coil-shaped polarization preserving fiber 30, to achieve a highly accurate measurement.

Abstract: A timing window (TW) representing a time zone where a signal transition possibly occurs in a time axis is generated for each of input signals in input terminals in a multi-input logic cell based on a signal transition timing in each of the input terminals. An overlap between the timing windows (TW) of input signals is detected, and a circuit delay time is calculated by selectively using one of a synchronous transition time and an asynchronous transition time in accordance with the overlap between the timing windows (TW). These processing steps are sequentially repeated to eliminate an optimistic or pessimistic analysis in the calculation of delay times in the multi-input logic cell.

Abstract: In a bearing device 1, annular recesses 3a and 6a that house a thrust bearing 7 are formed in side surfaces of a housing 3 and a cap 6, a rotation preventing protrusion 12b is provided in an outer periphery of a lower side half-split thrust bearing 12 in the thrust bearing 7, and a rotation preventing groove 6b into which the rotation preventing protrusion 12b fits is formed in the annular recess 6a formed in the cap 6. The rotation preventing groove 6b is formed to be deeper than the annular recess 6a, and in a surface of the lower side half-split thrust bearing 12 on the side of the crank arm, a groove 12c is formed from the rotation preventing protrusion 12b to an inner peripheral portion of the lower side half-split thrust bearing 12. This can prevent partial contact of the thrust bearing, and prevent breakage due to stress concentration as much as possible.

Abstract: A semiconductor device includes: a semiconductor element (1) having an internal circuit (17); and electrode pads (22, 22, . . . ) provided for the semiconductor element (1). The electrode pads (22, 22, . . . ) are electrically connected to the internal circuit (17) via control portions (31) for controlling electrical connection between the electrode pads (22, 22, . . . ) and the internal circuit (17).

Abstract: An optical voltage transformer is connected with an external electric device and includes a primary electrode to which a measured voltage is applied by the external electric device, a first secondary electrode provided oppositely to the primary electrode, an insulation layer provided between the primary and first secondary electrodes and constituting an insulation cylinder integrally formed with the primary and first secondary electrodes, a ground layer provided on an outer circumference of the insulation cylinder and around the first secondary electrode for securing a capacitance by interposing the insulation layer between the ground layer and the first secondary electrode, and an electro-optic element for measuring a voltage between the first secondary electrode and the ground layer.

Abstract: A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the cutting region; a first interlayer insulating film formed in the scribe region on the semiconductor substrate; a first dummy pattern made of conductive material and formed in the first interlayer insulating film in the cutting region; and a second dummy pattern made of conductive material and formed in the first interlayer insulating film in each of the non-cutting regions. The ratio, per unit area, of the area of the first dummy pattern to the area of the cutting region is lower than the ratio, per unit area, of the area of the second dummy pattern to the area of the non-cutting regions.

Abstract: The present invention is useful for achieving a reduction in weight and for attaining increased strength in not only electronic devices and domestic electric devices but also various parts and structures. As a pretreatment, a rib (3) is dipped in an aqueous solution of ammonia, hydrazine, a hydrazine derivative, or a water-soluble amine compound. A metal frame (2) is inserted into an injection mold for forming ribs (3) by injection molding. A thermoplastic resin composition is injected to the surface of the metal frame (2) by injection molding to form ribs (3). In the housing of a casing cover (1) thus formed, the metal frame (2) and the ribs (3) made of the thermoplastic resin composition are integrally bonded together. Thus, the housing improves strength and external appearance. Moreover, a complicated configuration and structure can be formed in the housing.

Abstract: An electron-emitting device includes an emitter section composed of a dielectric material, a lower electrode disposed on the lower side of the emitter section, and an upper electrode disposed on the upper side of the emitter section so as to be opposed to the lower electrode with the emitter section therebetween, electrons being emitted from the emitter section through the upper electrode by the application of a drive voltage between the lower electrode and the upper electrode, wherein the upper electrode is provided with a plurality of through-holes which expose the emitter section and which have an average diameter of 10 nm or more and less than 100 nm, and a peripheral portion of each through-hole facing the emitter section is separated at a predetermined distance from the emitter section.

Abstract: An endoscope system has a scanner, a projector, and a measurement processor. The scanner is configured to scan light that passes through an optical fiber over a target by directing the light emitted from the distal end of an endoscope. The projector is configured to project a pattern on the target by switching on and off the light during scanning. Then, the measurement processor acquires a three dimensional (3-D) profile of the target on the basis of the shape of the pattern projected on the target.

Abstract: A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are formed around an N type diffusion layer as a base region. One of the P type diffusion layers is formed to have a lower impurity concentration and a narrower diffusion width than the other P type diffusion layer. In this structure, when a vertical PNP transistor is turned on, a region where the former P type diffusion layer is formed mainly serves as a parasite current path. Thus, a parasitic transistor constituted of a substrate, an N type buried layer and a P type buried layer is prevented from turning on, and a leakage current into the substrate is prevented.

Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.

Abstract: An optical device comprises a first optical system, a second optical system, a shading unit, and a diffraction grating. The first optical system transforms incident light to parallel light. The second optical system transforms incident light to parallel light. An optical axis of the second optical system is different from an optical axis of the first optical system. The shading unit has transmission areas having slit forms and shading areas having strip forms. The transmission areas and the shading areas are alternately arranged. The diffraction grating deflects the light transmitted by the transmission areas in a predetermined direction. Part of the incident light through the first optical system passes through the transmission areas, and the rest are shaded by the shading areas. Part of the incident light through the second optical system passes through the transmission areas, and the rest are shaded by the shading areas.

Abstract: The present invention is useful for achieving a reduction in weight and for attaining increased strength in not only electronic devices and domestic electric devices but also various parts and structures. As a pretreatment, a rib (3) is dipped in an aqueous solution of ammonia, hydrazine, a hydrazine derivative, or a water-soluble amine compound. A metal frame (2) is inserted into an injection mold for forming ribs (3) by injection molding. A thermoplastic resin composition is injected to the surface of the metal frame (2) by injection molding to form ribs (3). In the housing of a casing cover (1) thus formed, the metal frame (2) and the ribs (3) made of the thermoplastic resin composition are integrally bonded together. Thus, the housing improves strength and external appearance. Moreover, a complicated configuration and structure can be formed in the housing.

Abstract: A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the cutting region; a first interlayer insulating film formed in the scribe region on the semiconductor substrate; a first dummy pattern made of conductive material and formed in the first interlayer insulating film in the cutting region; and a second dummy pattern made of conductive material and formed in the first interlayer insulating film in each of the non-cutting regions. The ratio, per unit area, of the area of the first dummy pattern to the area of the cutting region is lower than the ratio, per unit area, of the area of the second dummy pattern to the area of the non-cutting regions.

Abstract: An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.

Abstract: Circuits under electrode terminals and a nonconductor layer of the electrode terminals in semiconductor devices are prevented from being damaged during a test, such as a burn-in test, on the semiconductor devices formed on a wafer. Alignment patterns provided on the semiconductor wafer have detector electrode terminals and conductor electrode terminals. A detector electrode terminal surrounds a conductor electrode terminal separated by a gap from the detector electrode terminals and a portion of the surrounding detector electrode terminal is open.