Patents by Inventor Masaro Tamatsuka

Masaro Tamatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11248306
    Abstract: An anodic-oxidation equipment for forming a porous layer on a substrate to be treated, including: an electrolytic bath filled with an electrolytic solution; an anode and a cathode disposed in the electrolytic solution; and a power supply for applying current between the anode and the cathode in the electrolytic solution, wherein the anode is the substrate to be treated, and the cathode is a silicon substrate having a surface on which a nitride film is formed. This provides a cathode material in anodic-oxidation for forming porous silicon by an electrochemical reaction in an HF solution, the cathode material having a resistance to electrochemical reaction in an HF solution and no metallic contamination, etc., and furthermore, being less expensive than a conventional cathode material. Furthermore, high-quality porous silicon is provided at a lower cost than has been conventional.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 15, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Masaro Tamatsuka
  • Publication number: 20210238762
    Abstract: An anodic-oxidation equipment for forming a porous layer on a substrate to be treated, including: an electrolytic bath filled with an electrolytic solution; an anode and a cathode disposed in the electrolytic solution; and a power supply for applying current between the anode and the cathode in the electrolytic solution, wherein the anode is the substrate to be treated, and the cathode is a silicon substrate having a surface on which a nitride film is formed. This provides a cathode material in anodic-oxidation for forming porous silicon by an electrochemical reaction in an HF solution, the cathode material having a resistance to electrochemical reaction in an HF solution and no metallic contamination, etc., and furthermore, being less expensive than a conventional cathode material. Furthermore, high-quality porous silicon is provided at a lower cost than has been conventional.
    Type: Application
    Filed: April 2, 2019
    Publication date: August 5, 2021
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi OHTSUKI, Masaro TAMATSUKA
  • Patent number: 7326658
    Abstract: The present invention provides a method for producing a nitrogen-doped annealed wafer, wherein before a wafer sliced from a silicon single crystal doped with at least nitrogen and polished is subjected to a high temperature heat treatment at 1100° C. to 1350° C. in an atmosphere of argon, hydrogen or a mixed gas thereof, a step of maintaining the wafer at a temperature lower than the treatment temperature of the high temperature heat treatment is conducted to allow growth of oxygen precipitation nuclei having such a size that the nuclei should be annihilated by the high temperature heat treatment to such a size that the nuclei should not be annihilated by the high temperature heat treatment, and then the high temperature heat treatment is performed.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: February 5, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Makoto Iida, Masaro Tamatsuka
  • Patent number: 7189293
    Abstract: The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: March 13, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Hiroshi Takeno, Ken Aihara
  • Patent number: 7153785
    Abstract: The present invention provides method of producing an annealed wafer wherein a silicon single crystal wafer produced by the Czochralski (CZ) method is subjected to a high temperature annealing in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, during the annealing the silicon single crystal wafer is supported by a supporting jig only in a central side region of the wafer except for 5 mm or more from a peripheral end of the wafer, and before performing the high temperature annealing, a pre-annealing is performed at a temperature less than the temperature of the high temperature annealing to grow oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein slip dislocations generated in a high temperature annealing can be suppressed even in the case of a silicon single crystal wafer having a large diameter of 300 mm or more, and provided the annealed wafer.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: December 26, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu
  • Patent number: 7147711
    Abstract: The present invention provides a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 ?·cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less, and a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 ?·cm or more and an initial interstitial oxygen concentration of 8 ppma or less and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment to form an oxide precipitate layer in a bulk portion of the wafer, as well as silicon wafers produced by these production methods.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: December 12, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masaro Tamatsuka, Wei Feig Qu, Norihiro Kobayashi
  • Patent number: 7011717
    Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1–60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 ?m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 14, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
  • Patent number: 6878645
    Abstract: Provided is a process for manufacturing a silicon wafer employing heat treatment which is applied on the silicon wafer in inert gas atmosphere represented by Ar annealing to annihilate Grown-in defects in a surface layer region of the silicon wafer as well as to cause no degradation of haze and micro-roughness on a surface thereof. In a process for manufacturing a silicon wafer having a step of heat treating the silicon wafer in inert gas atmosphere, using a purge box with which the silicon wafer heat treated in the inert gas atmosphere can be unloaded to outside a reaction tube of a heat treatment furnace without being put into contact with the open air, the purge box is filled with mixed gas of nitrogen and oxygen or 100% oxygen gas, and the heat treated silicon wafer is unloaded into the purge box.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: April 12, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Shoji Akiyama, Masaro Tamatsuka, Masaru Shinomiya, Yuichi Matsumoto
  • Publication number: 20050025691
    Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 ?m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 3, 2005
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
  • Patent number: 6841450
    Abstract: The present invention provides an annealed wafer manufacturing method using a heat treatment method causing no change in resistivity of a wafer surface even when a silicon wafer having boron deposited on a surface thereof from an environment is subjected to heat treatment in an insert gas atmosphere and enabling the heat treatment in an ordinary diffusion furnace not requiring a sealed structure for increasing airtightness nor any specific facility such as explosion-proof facility. The present invention also provides an annealed wafer in which a boron concentration in the vicinity of a surface thereof is constant and crystal defects are annihilated.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: January 11, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Makoto Iida
  • Publication number: 20040231759
    Abstract: The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100-1350° C. for 10-600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.
    Type: Application
    Filed: December 24, 2003
    Publication date: November 25, 2004
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Hiroshi Takeno, Ken Aihara
  • Patent number: 6809015
    Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: October 26, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
  • Patent number: 6805743
    Abstract: According to the present invention, there are provided a method for producing a silicon single crystal wafer which contains oxygen induced defects by subjecting a silicon single crystal wafer containing interstitial oxygen to a heat treatment wherein the heat treatment includes at least a step of performing a heat treatment using a resistance-heating type heat treatment furnace and a step of performing a heat treatment using a rapid heating and rapid cooling apparatus, and a silicon single crystal wafer produced by the method. There can be provided a method for producing a silicon single crystal wafer which has a DZ layer of higher quality compared with a conventional wafer in a wafer surface layer part and has oxygen induced defects at a sufficient density in a bulk part and the silicon single crystal wafer.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: October 19, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya
  • Patent number: 6802899
    Abstract: There is provided a manufacturing process for a CZ silicon single crystal wafer which is subjected to heat treatment wherein slip resistance of a portion of the CZ silicon single crystal wafer in contact with a heat treatment boat is improved with extreme simplicity, convenience and very low cost. A silicon single crystal rod is grown by means of a Czochralski method in a condition that an OSF ring region is formed in a peripheral region of the silicon single crystal rod and the grown silicon signal crystal rod is processed into silicon single crystal wafers, whereby the silicon single crystal wafer is obtained such that when the silicon single crystal wafer is subjected to heat treatment, at least a portion of the silicon single crystal wafer in contact between the wafer and the boat is formed of an OSF ring region.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: October 12, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Masaro Tamatsuka
  • Publication number: 20040192071
    Abstract: The present invention provides method of producing an annealed wafer wherein a silicon single crystal wafer produced by the Czochralski (CZ) method is subjected to a high temperature annealing in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100-1350° C. for 10-600 minutes, during the annealing the silicon single crystal wafer is supported by a supporting jig only in a central side region of the wafer except for 5 mm or more from a peripheral end of the wafer, and before performing the high temperature annealing, a pre-annealing is performed at a temperature less than the temperature of the high temperature annealing to grow oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein slip dislocations generated in a high temperature annealing can be suppressed even in the case of a silicon single crystal wafer having a large diameter of 300 mm or more, and provided the annealed wafer.
    Type: Application
    Filed: February 23, 2004
    Publication date: September 30, 2004
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feing Qu
  • Publication number: 20040023518
    Abstract: Provided is a process for manufacturing a silicon wafer employing heat treatment which is applied on the silicon wafer in inert gas atmosphere represented by Ar annealing to annihilate Grown-in defects in a surface layer region of the silicon wafer as well as to cause no degradation of haze and micro-roughness on a surface thereof. In a process for manufacturing a silicon wafer having a step of heat treating the silicon wafer in inert gas atmosphere, using a purge box with which the silicon wafer heat treated in the inert gas atmosphere can be unloaded to outside a reaction tube of a heat treatment furnace without being put into contact with the open air, the purge box is filled with mixed gas of nitrogen and oxygen or 100% oxygen gas, and the heat treated silicon wafer is unloaded into the purge box.
    Type: Application
    Filed: January 10, 2003
    Publication date: February 5, 2004
    Inventors: Norihiro Kobayashi, Shoji Akiyama, Masaro Tamatsuka, Masaru Shinomiya, Yuichi Matsumoto
  • Patent number: 6680260
    Abstract: There is provided a method of producing a bonded SOI wafer wherein a silicon single crystal ingot is grown according to Czochralski method, the single crystal ingot is then sliced to produce a silicon single crystal wafer, the silicon single crystal wafer is subjected to heat treatment in a non-oxidizing atmosphere at a temperature of 1100° C. to 1300° C. for one minute or more and continuously to a heat treatment in an oxidizing atmosphere at a temperature of 700° C. to 1300° C. for one minute or more without cooling the wafer to a temperature less than 700° C. to provide a silicon single crystal wafer wherein a silicon oxide film is formed on the surface, and the resultant wafer is used as the bond wafer, and a bonded SOI wafer produced by the method. There can be provided a SOI wafer that has a SOI layer having few crystal defects, good surface roughness and high quality in high productivity, in high yield and with low cost.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: January 20, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Shoji Akiyama, Masaro Tamatsuka
  • Publication number: 20040003769
    Abstract: The present invention provides a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 &OHgr;·cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less, and a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 &OHgr;·cm or more and an initial interstitial oxygen concentration of 8 ppma or less and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment to form an oxide precipitate layer in a bulk portion of the wafer, as well as silicon wafers produced by these production methods.
    Type: Application
    Filed: March 18, 2003
    Publication date: January 8, 2004
    Inventors: Masaro Tamatsuka, Wei Feig Qu, Norihiro Kobayashi
  • Patent number: 6670261
    Abstract: There is provided a manufacturing process for an annealed wafer capable of reducing boron contamination occurring while annealing is performed in a state where a wafer surface after cleaning is exposed to a gas in Ar atmosphere to suppress a change in resistivity due to an increase in a boron concentration in the vicinity of the wafer surface after annealing and manufacture an annealed wafer in which a difference in a boron concentration between a surface layer portion thereof and a bulk portion thereof is essentially not a problem even if a silicon wafer having a comparative low boron concentration (1×1016 atoms/cm3 or less) is used as the annealed wafer. The manufacturing process for an annealed wafer comprises: cleaning a silicon wafer; and loading the silicon wafer into a heat treatment furnace to heat-treat the silicon wafer in an Ar atmosphere, wherein an aqueous solution including hydrofluoric acid is used as a final cleaning liquid in the cleaning.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: December 30, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Shoji Akiyama, Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya
  • Publication number: 20030196588
    Abstract: A silicon boat for supporting a silicon wafer during a heat treatment of the wafer, wherein a protective film consisting of a thermal oxide film is directly formed on a surface of the boat. A silicon boat is left in argon, hydrogen or a mixed gas of argon and hydrogen within a temperature range of 1000° C. or higher for 10 minutes or more to remove a native oxide film on the surface of the boat and then subjected to a heat treatment in an atmosphere containing oxygen to grow a protective film consisting of an oxide film on the surface of the boat. By using this silicon boat, silicon wafers are subjected to a heat treatment in an atmosphere consisting of argon or a mixed gas of argon and hydrogen. Thus, there are provided a boat for heat treatment of wafer and a method for heat treatment of wafer, in which metal contamination is not caused in the wafer, and falling off of the protective film, damage of the wafer surface and generation of particles are prevented.
    Type: Application
    Filed: January 21, 2003
    Publication date: October 23, 2003
    Inventors: Norihiro Kobayashi, Shoji Akiyama, Masaro Tamatsuka, Masaru Shinomiya