Abstract: An object of the present disclosure is to provide a technique capable of relaxing the stress to be applied around the attachment hole of the resin case at the time of fixing the resin case accommodating the semiconductor element to the heat dissipation component with a bolt. A semiconductor device includes a base plate, a heat dissipation component, and a resin case. In a state where the resin case is disposed on the heat dissipation component via the base plate, the resin case is attached to the heat dissipation component with a bolt. The resin case has a recess portion, an attachment hole formed below the recess portion, and at least one groove formed between a wall portion on an inner peripheral side forming the recess portion and the attachment hole. One end of the at least one groove reaches an outer peripheral end of the resin case.

Abstract: A semiconductor device includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type on the first region, and a third silicon carbide region of a second conductivity type on the second region. Fourth and fifth silicon carbide region of the first conductivity type are on the third region. A first electrode has a first portion between the fourth region and fifth region in a first direction. A metal silicide layer is between the first portion and the third region, between the first portion and the fourth region in the first direction, and between the first portion and the fifth silicon carbide region in the first direction.

Abstract: Various illustrative aspects are directed to a data storage device, comprising: one or more disks; an actuator assembly comprising a head, and configured to position the head over a corresponding disk surface; and one or more processing devices, the head comprising: a write element; a laser unit; and a fly height control element, and wherein the one or more processing devices are configured to: iteratively perform spiral write operations of spiral patterns comprising a plurality of sync marks with the head on the corresponding disk surface, wherein the spiral write operations are performed at: a plurality of values of laser pre-bias current, write backoff, and/or start disk phase; detect pattern signal amplitudes of the spiral patterns on the corresponding disk surface; and determine a relation of write backoff to laser pre-bias current for the head, based on the pattern signal amplitudes of the spiral patterns.

Abstract: Various illustrative aspects are directed to a data storage device, comprising: one or more disks; an actuator assembly comprising a head, and configured to position the head over a corresponding disk surfaces; and one or more processing devices, wherein the head comprises: a write element; a laser unit; and a fly height control element, and wherein the one or more processing devices are configured to: iteratively perform write start operations of write start patterns with the head on the corresponding disk surface, at a plurality of values of at least one of laser pre-bias current, and write backoff; detect pattern signal amplitudes of the write start patterns on the corresponding disk surface; and determine a relation of write backoff to laser pre-bias current for the head, based at least in part on the pattern signal amplitudes.

Abstract: A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.

Abstract: Provided are a semiconductor device and an inverter device with a decrease in yield being suppressed by preventing the adhesive from leaking into the inside of the semiconductor device. A heat sink, a wiring board provided on the heat sink, a semiconductor chip provided on the wiring board, a case housing provided on the heat sink so as to surround the wiring board and the semiconductor chip, an adhesive that adheres a lower surface joint portion of the case housing and an upper surface joint portion of the heat sink, a sealing material that fills the case housing and covers the wiring board and the semiconductor chip, and a convex portion provided on the lower surface joint portion of the case housing or the upper surface joint portion of the heat sink, that separates the adhesive from the sealing material are included.

Abstract: A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.

Abstract: According to one embodiment, a semiconductor device includes a first element region. The first element region includes first, second, and third semiconductor regions, and first, and second conductive layers. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the first conductive layer crosses a first direction from the second partial region toward the first partial region. The third partial region is between the second partial region and the second conductive layer in the second direction. The second semiconductor region includes a first semiconductor portion. The first semiconductor portion is between the first partial region and the first conductive layer in the second direction. At least a portion of the third semiconductor region is between the first partial region and the first semiconductor portion in the second direction.

Abstract: The semiconductor device includes a semiconductor element, a plurality of terminal electrodes, internal wiring, and a sealing material. The semiconductor element is mounted on a circuit pattern provided on an insulating substrate. The plurality of terminal electrodes are provided on a case in which the insulating substrate and the semiconductor element are contained. The internal wiring connects the semiconductor element and the plurality of terminal electrodes. The sealing material fills a space in the case. The internal wiring includes a plurality of circuit patterns, a plurality of metal blocks, and metal wire. The plurality of metal blocks are electrically connected to the respective circuit patterns. The metal wire connects the plurality of metal blocks and is bonded to the plurality of metal blocks at positions closer to an upper surface of the sealing material than surfaces of the plurality of circuit patterns.

Abstract: According to one embodiment, a semiconductor device includes a first element region. The first element region includes first, second, and third semiconductor regions, and first, and second conductive layers. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the first conductive layer crosses a first direction from the second partial region toward the first partial region. The third partial region is between the second partial region and the second conductive layer in the second direction. The second semiconductor region includes a first semiconductor portion. The first semiconductor portion is between the first partial region and the first conductive layer in the second direction. At least a portion of the third semiconductor region is between the first partial region and the first semiconductor portion in the second direction.

Abstract: An object of the present disclosure is to provide a technique capable of relaxing the stress to be applied around the attachment hole of the resin case at the time of fixing the resin case accommodating the semiconductor element to the heat dissipation component with a bolt. A semiconductor device includes a base plate, a heat dissipation component, and a resin case. In a state where the resin case is disposed on the heat dissipation component via the base plate, the resin case is attached to the heat dissipation component with a bolt. The resin case has a recess portion, an attachment hole formed below the recess portion, and at least one groove formed between a wall portion on an inner peripheral side forming the recess portion and the attachment hole. One end of the at least one groove reaches an outer peripheral end of the resin case.

Abstract: The semiconductor device includes a semiconductor element, a plurality of terminal electrodes, internal wiring, and a sealing material. The semiconductor element is mounted on a circuit pattern provided on an insulating substrate. The plurality of terminal electrodes are provided on a case in which the insulating substrate and the semiconductor element are contained. The internal wiring connects the semiconductor element and the plurality of terminal electrodes. The sealing material fills a space in the case. The internal wiring includes a plurality of circuit patterns, a plurality of metal blocks, and metal wire. The plurality of metal blocks are electrically connected to the respective circuit patterns. The metal wire connects the plurality of metal blocks and is bonded to the plurality of metal blocks at positions closer to an upper surface of the sealing material than surfaces of the plurality of circuit patterns.

Abstract: A semiconductor device according to an embodiment includes first electrode; second electrode; silicon carbide layer between the first electrode and the second electrode, the silicon carbide layer having first and second plane, the silicon carbide layer including first silicon carbide region of first-conductivity-type, second silicon carbide region and third silicon carbide region between the first silicon carbide region and the first plane, fourth silicon carbide region between the second silicon carbide region and the first plane, the fourth silicon carbide region contacting the first electrode, fifth silicon carbide region between the second silicon carbide region and the third silicon carbide region, the fifth silicon carbide region having a higher first-conductivity-type impurity concentration than the first silicon carbide region, sixth silicon carbide region between the fifth silicon carbide region and the first plane, the sixth silicon carbide region contacting the first electrode; gate electrode facin

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; and a gate insulating layer which is provided between the silicon carbide layer and the gate electrode and includes a first silicon oxide layer and a second silicon oxide layer provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness. The second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; and a gate insulating layer which is provided between the silicon carbide layer and the gate electrode and includes a first silicon oxide layer and a second silicon oxide layer provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness. The second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.

Abstract: A semiconductor device according to an embodiment includes first electrode; second electrode; silicon carbide layer between the first electrode and the second electrode, the silicon carbide layer having first and second plane, the silicon carbide layer including first silicon carbide region of first-conductivity-type, second silicon carbide region and third silicon carbide region between the first silicon carbide region and the first plane, fourth silicon carbide region between the second silicon carbide region and the first plane, the fourth silicon carbide region contacting the first electrode, fifth silicon carbide region between the second silicon carbide region and the third silicon carbide region, the fifth silicon carbide region having a higher first-conductivity-type impurity concentration than the first silicon carbide region, sixth silicon carbide region between the fifth silicon carbide region and the first plane, the sixth silicon carbide region contacting the first electrode; gate electrode facin

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; a first silicon carbide region; second and third silicon carbide regions between the first silicon carbide region and the first plane; a fourth silicon carbide region between the second silicon carbide region and the first plane; a first and second gate electrodes; a suicide layer on the fourth silicon carbide region; a first electrode on the first plane having a first portion and a second portion, the first portion being in contact with the first silicon carbide region, the second portion being in contact with the suicide layer; a second electrode on the second plane; and an insulating layer between the first portion and the second portion having a first side surface and a second side surface, an angle of the first side surface being smaller than that of the second side surface.

Abstract: A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; a first silicon carbide region; second and third silicon carbide regions between the first silicon carbide region and the first plane; a fourth silicon carbide region between the second silicon carbide region and the first plane; a first and second gate electrodes; a suicide layer on the fourth silicon carbide region; a first electrode on the first plane having a first portion and a second portion, the first portion being in contact with the first silicon carbide region, the second portion being in contact with the suicide layer; a second electrode on the second plane; and an insulating layer between the first portion and the second portion having a first side surface and a second side surface, an angle of the first side surface being smaller than that of the second side surface.

Abstract: According to an embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a third semiconductor region, fourth semiconductor regions, and a first electrode. The second semiconductor region is provided on the first semiconductor region. The second semiconductor region includes a first portion and a second portion connected to the first portion in a first direction parallel to the first surface of the substrate. A conductivity type of the second semiconductor region is a second conductivity type. The first electrode is provided on the first portion of the second semiconductor region, the third semiconductor region, and the fourth semiconductor regions and is in contact with the first portion of the second semiconductor region.