Patents by Inventor Masaru Furukawa
Masaru Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190088775Abstract: According to an embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a third semiconductor region, fourth semiconductor regions, and a first electrode. The second semiconductor region is provided on the first semiconductor region. The second semiconductor region includes a first portion and a second portion connected to the first portion in a first direction parallel to the first surface of the substrate. A conductivity type of the second semiconductor region is a second conductivity type. The first electrode is provided on the first portion of the second semiconductor region, the third semiconductor region, and the fourth semiconductor regions and is in contact with the first portion of the second semiconductor region.Type: ApplicationFiled: March 12, 2018Publication date: March 21, 2019Inventor: Masaru Furukawa
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Patent number: 9887285Abstract: A semiconductor device comprises a silicon carbide layer, a first electrode, a second electrode, and a gate. The silicon carbide layer has first region of first conductivity type between the first and second electrodes and also the gate and second electrode. A second region of the first type is between the first electrode and the first region. A third region of second conductivity type is between the first electrode and the second region. A fourth region of the first type is between the first electrode and the third region. A fifth region of the first type is between the gate and the second region. The third region is between the fourth and fifth regions. A sixth region of the first type contacts the first electrode and is between the second region and this electrode. An insulation layer is between the gate and the third region and also the fifth region.Type: GrantFiled: February 27, 2017Date of Patent: February 6, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tsuyoshi Oota, Masaru Furukawa
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Publication number: 20170271507Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a p-type first silicon carbide region between the first electrode and the second electrode, an n-type second silicon carbide region between the first electrode and the first silicon carbide region, a third silicon carbide region, containing an n-type impurity which is different from an n-type impurity in the second silicon carbide region, between the first electrode and the first silicon carbide region and an n-type fourth silicon carbide region between the first silicon carbide region and the second electrode. A third electrode is in the first silicon carbide region, the second silicon carbide region, and the fourth silicon carbide region and spaced therefrom by an insulating film.Type: ApplicationFiled: August 22, 2016Publication date: September 21, 2017Inventors: Takuma SUZUKI, Masaru FURUKAWA, Hiroshi KONO
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Publication number: 20170077285Abstract: A semiconductor device includes a SiC layer having a first surface, a gate insulating film on the first surface, a gate electrode on the gate insulating film, a first SiC region of a first conductivity type in the SiC layer, a second SiC region of a second conductivity type in the first SiC region, a third SiC region of the first conductivity type in the second SiC region, wherein a boundary between the second SiC region and the third SiC region, and the first surface forms a first angle, and a fourth SiC region of the first conductivity type in the third SiC region, having an impurity concentration of the first conductivity type higher than that of the third SiC region, wherein a boundary between the third SiC region and the fourth SiC region, and the first surface forms a second angle that is smaller than the first angle.Type: ApplicationFiled: March 7, 2016Publication date: March 16, 2017Inventors: Junichi UEHARA, Masaru FURUKAWA, Hiroshi KONO, Takuma SUZUKI
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Publication number: 20160276441Abstract: A semiconductor device includes an SiC substrate including a first surface and a second surface, the SiC substrate having a first SiC region of a first conductivity type at the first surface, and a second SiC region of a second conductivity type between the first SiC region and the second surface, an insulating film on the first surface around an element region of the semiconductor device and in contact with the first SiC region, a first electrode on the insulating film and comprising a contact electrically connected to the first SiC region, and a second electrode in contact with the second surface. A first conductivity type impurity concentration of the first SiC region that is directly under a center portion of the contact is greater than a first conductivity type impurity concentration of the first SiC region that is directly under a peripheral portion of the contact.Type: ApplicationFiled: August 31, 2015Publication date: September 22, 2016Inventor: Masaru FURUKAWA
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Patent number: 9412825Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.Type: GrantFiled: August 29, 2014Date of Patent: August 9, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
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Patent number: 9311945Abstract: Embodiments of the present invention generally relate to a MAMR head. The MAMR head includes an STO and an embedded contact sensor (ECS). The STO and the ECS are electrically connected in series and are connected to the same terminals. During operation, the current applied to the STO is controlled with respect to a change in resistance of the ECS.Type: GrantFiled: November 6, 2013Date of Patent: April 12, 2016Assignee: HGST NETHERLANDS B.V.Inventors: Kenichiro Takahashi, Junguo Xu, Jianhua Li, Masaru Furukawa
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Publication number: 20160079410Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface.Type: ApplicationFiled: March 3, 2015Publication date: March 17, 2016Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI
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Patent number: 9202528Abstract: Embodiments of the present invention generally relate to a microwave assisted magnetic recording (MAMR) head. The MAMR head includes a main pole, a trailing shield, and a spin torque oscillator (STO) disposed between the main pole and the trailing shield. The STO is recessed from an air bearing surface.Type: GrantFiled: September 27, 2013Date of Patent: December 1, 2015Assignee: HGST NETHERLANDS B.V.Inventors: Masaru Furukawa, Jianhua Li, Masato Matsubara, Masato Shiimoto
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Publication number: 20150263152Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.Type: ApplicationFiled: August 29, 2014Publication date: September 17, 2015Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Takako MOTAI
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Publication number: 20150263179Abstract: A semiconductor device includes a first electrode, a second electrode, a first conductivity-type first semiconductor region between the first electrode and the second electrode, a first conductivity-type second semiconductor region between the first electrode and the first semiconductor region, the second semiconductor region having a dopant concentration that is higher than a dopant concentration of the first semiconductor region, the second semiconductor region including a silicide layer in contact with the first electrode, and a second conductivity-type third semiconductor region between the first semiconductor region and the second electrode.Type: ApplicationFiled: August 6, 2014Publication date: September 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaru FURUKAWA, Hideo YOSHIHASHI
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Publication number: 20150263700Abstract: According to one embodiment, a semiconductor device includes a GaN-based semiconductor layer, a resonator that uses a first portion of the GaN-based semiconductor layer as a piezoelectric layer to resonate, and a transistor that uses a second portion of the GaN-based semiconductor layer as a channel layer.Type: ApplicationFiled: September 2, 2014Publication date: September 17, 2015Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Yoshikazu SUZUKI
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Publication number: 20150124353Abstract: Embodiments of the present invention generally relate to a MAMR head. The MAMR head includes an STO and an embedded contact sensor (ECS). The STO and the ECS are electrically connected in series and are connected to the same terminals. During operation, the current applied to the STO is controlled with respect to a change in resistance of the ECS.Type: ApplicationFiled: November 6, 2013Publication date: May 7, 2015Applicant: HGST NETHERLANDS B.V.Inventors: Kenichiro TAKAHASHI, Junguo XU, Jianhua LI, Masaru FURUKAWA
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Patent number: 9007724Abstract: Embodiments disclosed herein generally relate to the data storage field and hard disk drives (HDD) using microwave assisted magnetic recording (MAMR) technology. Aspects of the preferred embodiments are to prevent the breakdown of spin torque oscillators (STO) due to large amounts of current flowing through the STO during head/disk contact. A magnetic head slider is disposed above and spaced apart from a disk. A STO is formed on a section of the magnetic head slider. Two electrodes are coupled to the STO, and one electrode has a higher potential than the other electrode. A preamplifier is adapted to send a current through the two electrodes, resulting in the higher potential electrode protruding closer to the disk than the lower potential electrode. Current then flows from one electrode to the disk without flowing through the STO, and breakdown of the STO is prevented.Type: GrantFiled: June 12, 2014Date of Patent: April 14, 2015Assignee: HGST Netherlands B.V.Inventors: Masaru Furukawa, Junguo Xu, Masato Shiimoto, Jianhua Li
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Publication number: 20150092292Abstract: Embodiments of the present invention generally relate to a microwave assisted magnetic recording (MAMR) head. The MAMR head includes a main pole, a trailing shield, and a spin torque oscillator (STO) disposed between the main pole and the trailing shield. The STO is recessed from an air bearing surface.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: HGST Netherlands B.V.Inventors: Masaru FURUKAWA, Jianhua LI, Masato MATSUBARA, Masato SHIIMOTO
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Publication number: 20150076506Abstract: This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer.Type: ApplicationFiled: March 17, 2014Publication date: March 19, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida
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Patent number: 8885274Abstract: A method, apparatus, and system are provided for implementing enhanced surface analysis test (SAT) function for microwave assisted magnetic recording (MAMR) hard disk drives (HDDs) using embedded contact sensor (ECS) and spin-torque oscillator (STO) signals. A preamplifier circuit receives the embedded contact sensor (ECS) and spin-torque oscillator (STO) signals and compares the received ECS and STO signals to identify magnetic disk media defects including bumps or thermal-asperity (TA) defects and pits or hole defects.Type: GrantFiled: October 18, 2013Date of Patent: November 11, 2014Assignee: HGST Netherlands B.V.Inventors: Masaru Furukawa, Junguo Xu, Jianhua Li, Makoto Satou, Kenichiro Takahashi
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Patent number: 8873191Abstract: An embedded contact sensor (ECS) element for fly-height control and touchdown detection. An embedded contact sensor (ECS) element with a resistance that changes with a temperature change, which senses a clearance change between a head slider and a disk of a disk drive. A resistance measurement section, within said head IC, that determines a value of direct current resistance (DCR) of said ECS element, wherein said value of DCR changes with a temperature change, wherein said temperature change is caused by an air bearing cooling and frictional induced heating at a head disk interface. A resistance slope to fly-height conversion section that dynamically determines a target fly-height value for said head slider over said disk based on changes in said value of DCR.Type: GrantFiled: March 14, 2013Date of Patent: October 28, 2014Assignee: HGST Netherlands B.V.Inventors: Jianhua Li, Kenichi Kuramoto, Toshiya Shiramatsu, Yuichi Aoki, Masaru Furukawa, Yuichiro Sano
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Publication number: 20140268386Abstract: An embedded contact sensor (ECS) element for fly-height control and touchdown detection. An embedded contact sensor (ECS) element with a resistance that changes with a temperature change, which senses a clearance change between a head slider and a disk of a disk drive. A resistance measurement section, within said head IC, that determines a value of direct current resistance (DCR) of said ECS element, wherein said value of DCR changes with a temperature change, wherein said temperature change is caused by an air bearing cooling and frictional induced heating at a head disk interface. A resistance slope to fly-height conversion section that dynamically determines a target fly-height value for said head slider over said disk based on changes in said value of DCR.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: HGST Netherlands B.V.Inventors: Jianhua Li, Kenichi Kuramoto, Toshiya Shiramatsu, Yuichi Aoki, Masaru Furukawa, Yuichiro Sano
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Patent number: 8835288Abstract: A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing.Type: GrantFiled: February 28, 2012Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Masaru Furukawa, Hiroshi Kono, Takashi Shinohe