Patents by Inventor Masaru Ito

Masaru Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847232
    Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
  • Publication number: 20200338793
    Abstract: The present disclosure provides a foam molded product and a manufacturing method. The foam molded product is includes a foam body, an insert material having a display unit or a detection unit attached to the foam body, and a surface material affixed to a surface to which at least the insert material is attached. A manufacturing method includes: preparing a pair of molds including a first mold and a second mold; affixing an insert material and a surface material together such that the surface material is in contact with a molding surface of the first mold; closing the pair of molds; injecting a foam resin into a molding space formed by closing the molds; foaming the foam resin to form a foam body; opening the pair of molds; and removing a molded product in which the affixed part and the foam body are integrated.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 29, 2020
    Inventors: Tatsuo Ito, Kenji Okumura, Jun Sasaki, Daichi Hama, Masaru Terashita
  • Patent number: 10811393
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki
  • Patent number: 10790266
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Masahiro Yoshihara, Shinya Okuno, Shigeki Nagasaka
  • Publication number: 20200292922
    Abstract: A first optical system, a first mirror, a second optical system, a second mirror, and a third optical system are disposed in order on an optical axis from an image forming panel to a screen. A first optical axis of the first optical system, a second optical axis of the second optical system, and a third optical axis of the third optical system are formed in a U shape, and orientations of luminous fluxes of the first optical axis and the third optical axis are reversed. The first mirror, the second optical system, the second mirror, and the third optical system are held to make a second holding barrel with respect to the first optical system. The second holding barrel is rotationally moved in a rotational movement range of 45° with respect to a first holding barrel. In projecting portrait image instead of a landscape image, the second holding barrel is rotated in increments of 45° with respect to the first holding barrel.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Applicant: FUJIFILM Corporation
    Inventors: Masaru AMANO, Yukiko NAGATOSHI, Hironobu KAYANO, Kenji ITO
  • Publication number: 20200292923
    Abstract: A projector includes a projection lens and a projector body. In the projection lens, a U-shaped optical path is formed by optical axis to optical axis. A lens barrel is a U-shaped barrel. A housing of the projector body includes a storage section. The projection lens is supported rotatably about the optical axis with respect to the housing, in an up-down direction and a right-left direction of the housing perpendicular to the optical axis, between a first position where the projection lens is stored inside a storage section provided in the housing and a second position where the projection lens is protruding from the housing.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Applicant: FUJIFILM Corporation
    Inventors: Masaru AMANO, Yukiko NAGATOSHI, Hironobu KAYANO, Kenji ITO
  • Publication number: 20200292924
    Abstract: A first holding barrel, a first mirror bending a first optical axis of the first holding barrel at 90°, a second holding barrel, a second mirror bending a second optical axis of the second holding barrel at 90°, and a third holding barrel are disposed on an optical axis from a screen side to an image forming panel. A first connection member connects the first holding barrel including the first mirror to the second holding barrel to be rotationally movable in increments of 90°. A second connection member connects the second holding barrel and the second mirror to the third holding barrel to be rotationally movable in increments of 90°. An orientation of a display image of the image forming panel is changed based on rotational movement states of an optical axis of a first sensor and an optical axis of a second sensor to make an orientation of a projection image on the screen match an original image.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Applicant: FUJIFILM Corporation
    Inventors: Masaru AMANO, Yukiko NAGATOSHI, Hironobu KAYANO, Kenji ITO
  • Patent number: 10759781
    Abstract: The present invention provides a compound of general formula (I) (wherein, R1, X, p and q are as described in the present description and claims), or a pharmacologically acceptable salt thereof, and a pharmaceutical composition containing that compound.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: September 1, 2020
    Assignee: UBE INDUSTRIES, LTD.
    Inventors: Ken-ichi Komori, Akishi Ninomiya, Shigeru Ushiyama, Masaru Shinohara, Koji Ito, Tetsuo Kawaguchi, Yasunori Tokunaga, Hiroyoshi Kawada, Haruka Yamada, Yusuke Shiraishi, Masahiro Kojima, Masaaki Ito, Tomio Kimura
  • Publication number: 20200265902
    Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
  • Patent number: 10734360
    Abstract: A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
  • Publication number: 20200212314
    Abstract: An organic light-emitting device comprising: a first electrode; a second electrode; and an emission layer between the first electrode and the second electrode, wherein the emission layer comprising a first compound, a second compound, and a third compound, the first compound comprising at least one compound represented by one of Formulae 1-1 to 1-4, the second compound comprising at least one compound represented by one of Formulae 2-1 to 2-4, and the third compound includes at least one of a triphenylene group, a dibenzofuran group, a dibenzothiophene group, a fluorene group, a biscarbazole group, or any combination thereof, wherein a band gap between a highest occupied molecular orbital (HOMO) band energy level and a lowest unoccupied molecular orbital (LUMO) band energy level of the third compound is 3.3 eV or more. Formulae 1-1 to 1-4 and Formulae 2-1 to 2-4 are described herein.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 2, 2020
    Inventors: Masaki NUMATA, Masaru KINOSHITA, Mitsunori ITO, Wataru SOTOYAMA
  • Publication number: 20200202959
    Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.
    Type: Application
    Filed: August 29, 2019
    Publication date: June 25, 2020
    Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yumi TAKADA, Yasuhiro HIRASHIMA, Satoshi INOUE, Kensuke YAMAMOTO, Shouichi OZAKI, Taichi WAKUI, Fumiya WATANABE
  • Patent number: 10679710
    Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: June 9, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
  • Publication number: 20200161646
    Abstract: A nickel-hydrogen secondary battery includes an electrode group comprising a separator, a positive electrode, and a negative electrode, and the positive electrode contains a positive electrode active material including a base particle comprising a nickel hydroxide particle containing Mn in solid solution and a conductive layer comprising a Co compound and covering the surface of the base particle, wherein the X-ray absorption edge energy of Mn detected within 6500 to 6600 eV by measurement with an XAFS method is 6548 eV or higher.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: Takeshi Ito, Yuzo Imoto, Masaru Kihara, Takayuki Yano, Shigekazu Yasuoka, Shuuichi Doi, Takashi Yamazaki, Yuji Kataoka
  • Patent number: 10593649
    Abstract: A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
  • Publication number: 20200048598
    Abstract: The cell handling device includes a container having a section to store cells; a cell detection unit for detecting a cell stored in the section; a head device for conducting picking of cells, and transfer and release of the picked cells; a control unit; and a determination unit for making a determination of a cell state including at least one of the number, properties, and arrangement of the cells based on a detection result of the cell detection unit. The control unit causes the head device to execute, according to a state determination result obtained by the determination unit, one operation selected from among operation of picking all the cells stored in the section, operation of picking a part of the cells stored in the section, operation of picking a new cell and releasing the cell in the section, and operation of terminating processing of the section.
    Type: Application
    Filed: February 26, 2018
    Publication date: February 13, 2020
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Masaru SAKAMOTO, Saburo ITO, Takahiko KUMAGAI
  • Patent number: 10526497
    Abstract: The present invention provides a plating method capable of easily performing various decorative plating processes. The plating method includes a bulge forming process of forming a bulge on an object to be plated by ejecting ink drops of first UV-curable ink from an inkjet head such that the ejected ink drops land on the object, and a plating process of plating the object having the bulge formed thereon, after the bulge forming process. Also, in the bulge forming process, the bulge is formed such that a second surface of the bulge to be plated has surface roughness different from that of a first surface of the object to be plated.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: January 7, 2020
    Assignee: MIMAKI ENGINEERING CO., LTD.
    Inventors: Masaru Ohnishi, Toshiya Ito
  • Publication number: 20190385667
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Masaru Morohashi, Ryo Nagoshi, Yuan He, Yutaka Ito
  • Patent number: 10495114
    Abstract: A blower fan includes a plurality of blades radially extending from a boss provided at a rotary center and spaced apart from each other in the rotational direction, and a ring portion connecting outer peripheral ends of the blades in a ring shape. A radially outer end part at an end on an air-flow upstream side of the ring portion is positioned outward in a radial direction of a rotary shaft in the blower fan, as toward the air-flow upstream side. Thus, the blower can prevent the backflow air from being swirled, thereby reducing noise.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: December 3, 2019
    Assignee: DENSO CORPORATION
    Inventors: Toshikatsu Kondou, Youhei Kamiya, Masaru Kamiya, Takeshi Miyamoto, Masashi Matsukawa, Isao Kondoh, Takashi Ito, Kazuhiro Takeuchi
  • Patent number: 10482977
    Abstract: A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 19, 2019
    Assignee: TOSHIBA MEMEORY CORPORATION
    Inventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yasuhiro Hirashima