Abstract: In combining an analog terminal of an A/D converter with a digital terminal, the effect of the noise from the digital terminal is reduced. A semiconductor integrated circuit includes a high-speed external terminal, a low-speed external terminal, a high-speed analog switch, a low-speed analog switch, and an A/D converter. The high-speed external terminal is coupled to an input of the A/D converter via the high-speed analog switch, and the low-speed external terminal is coupled to the input of the A/D converter via the low-speed analog switch. A plurality of inputs of a plurality of low-speed digital input buffer circuits and a plurality of outputs of a plurality of low-speed digital output buffer circuits are coupled to a plurality of low-speed external terminals.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: There is provided a fuse module that holds trimming information for an internal oscillation circuit module. The fuse module includes information-writing fuse circuits to which trimming information is written depending on whether an information-writing fuse is blown; a reference fuse circuit for determining whether the information-writing fuse has been blown; and a current-to-voltage converter section. Since the reference fuse circuit and the current-to-voltage converter section are shared by the information-writing fuse circuits, the circuit area of the fuse module is greatly reduced.

Abstract: A microcontroller formed on a single chip semiconductor includes a central processing unit; an oscillator unit adapted to generate a system clock, and an electrical fuse unit including a control information for trimming a frequency of the oscillator unit. The central processing unit is operable to generate said control information which controls the oscillator unit, using an external clock from outside the microcontroller. The oscillator unit is trimmed by the control information for generating the system clock. Also, the central processing unit is capable of operating by the system clock.

Abstract: There is provided a fuse module that holds trimming information for an internal oscillation circuit module. The fuse module includes information-writing fuse circuits to which trimming information is written depending on whether an information-writing fuse is blown; a reference fuse circuit for determining whether the information-writing fuse has been blown; and a current-to-voltage converter section. Since the reference fuse circuit and the current-to-voltage converter section are shared by the information-writing fuse circuits, the circuit area of the fuse module is greatly reduced.

Abstract: A semiconductor integrated circuit capable of performing internal oscillation with high precision is provided. The semiconductor integrated circuit has a memory circuit, an oscillator circuit for generating an internal clock signal based on control information held in the memory circuit, a logic circuit for generating control information for causing the frequency of the internal clock signal to coincide with the frequency of an external clock signal, and an electric fuse circuit or a blow fuse circuit capable of storing the control information generated in the logic circuit and uses the internal clock signal for the synchronous operation of the internal circuit.

Abstract: There is provided a fuse module that holds trimming information for an internal oscillation circuit module. The fuse module includes information-writing fuse circuits to which trimming information is written depending on whether an information-writing fuse is blown; a reference fuse circuit for determining whether the information-writing fuse has been blown; and a current-to-voltage converter section. Since the reference fuse circuit and the current-to-voltage converter section are shared by the information-writing fuse circuits, the circuit area of the fuse module is greatly reduced.