Abstract: Disclosed is a method of manufacturing a semiconductor integrated circuit device which will not incur an increase in chip cost and a reduction in throughput, wherein the method includes a step of patterning a gate (electrode or wiring). With the method, a hard mask on the gate is patterned by a resist mask, and then the resist mask is removed. The gate material side surface is trimmed by using the hard mask under such dry etching conditions that no reaction product will be left on the gate material side surface to form an I-type gate.

Abstract: The present invention is provided to prevent yield reduction of semiconductor device in dry cleaning of semiconductor device manufacturing process. The electric action and chemical action due to plasma of a first gas generated by means of a plasma generating means and the physical action due to viscous friction force of high speed gas flow generated by means of a planar pad that is brought close to the main surface of a wafer are applied together for cleaning the main surface of the wafer. After cleaning, the wafer is exposed to plasma of a second gas in the same vacuum chamber and then transferred to the atmosphere.

Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.

Abstract: A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combination. The process is also preferably characterized by performing trimming and drying cleaning in a vacuum environment and may also include steps of inspecting dimensions and contamination in a vacuum environment.

Abstract: A dry cleaning device, wherein a pad is moved towards a surface of a wafer, cleaning gas is injected into a space formed between the pad and the wafer to generate a high-speed gas flow along the surface of the wafer whereby particles left on the surface of the wafer are removed with the high-speed gas flow. In addition, in order to assist this physical cleaning action, either a chemical or an electrical cleaning method such as a plasma additionally may be used.

Abstract: Disclosed is a process for fabricating a semiconductor device, which efficiently suppresses a damage layer formed on a base silicon substrate or an interconnection layer and removes a high resistivity layer in the formation of a contact hole, thereby reducing a contact resistance. The contact hole is formed in an etching step of reducing ion energy and an oxygen flow rate as an etching depth progresses, thereby suppressing the damage layer formed on the base. The reduction of the contact resistance is achieved by using a step of removing the high resistivity layer using hydrogen or a hydrogen-containing gas plasma.

Abstract: A method of dry cleaning surfaces of a semiconductor wafer includes the steps of placing a processed wafer in a vacuum environment and positioning a pad near each of a front surface and a back surface of the wafer. Cleaning gas is injected into a small clearance formed between each pad and the front and rear surfaces to generate a high-speed gas flow along the surface of the wafer. Particles left at the surfaces of the processed wafer are physically cleaned and removed with the high-speed gas flow. In order to assist this physical cleaning action, it is also possible to apply either a chemical cleaning method or an electrical cleaning method under application of plasma.

Abstract: With a view to providing a technique for highly-selective etching of Ru (ruthenium) using a photoresist as an etching mask, an Ru-film, which is an lower electrode material deposited on the side walls and bottom surface of a hole, is covered with a photoresist film, followed by isotropic dry etching in a gas atmosphere containing an ozone gas, whereby a portion of the Ru film outside of the hole is removed.

Abstract: A dry etching apparatus and method which can uniformly and stably generate a high-density plasma over a wide range, and can cope with increase of wafer diameter and making the pattern finer in etch processing of the fine pattern of a semiconductor device. The apparatus and method enables a magnitude of a magnetic field to be cyclically modulated when a substrate to be treated is etch processed. The cyclical modulation may be effected by cyclically modulating a coil current flowing to a solenoid coil.

Abstract: A chemical conversion treatment liquid which can stably form a phosphate-type chemical conversion film on a steel material for a joint portion of an oil well steel pipe containing 0.5-13% Cr is developed.

Abstract: A parallel plate ECR plasma processing system is able to extend a plasma density region capable of keeping a continuous, uniform state. In this system, a first magnetic field-forming means formed of a solenoid coil and a second magnetic field-forming means are provided so that a the distribution of a direction of a magnetic line of flux on the surface of a planar plate is controlled by a combined magnetic field from the first and second magnetic field-forming means thereby controlling the distribution in degree of the interactions of the magnetic field and an electromagnetic wave. This control ensures the uniformity of a plasma under high density plasma formation conditions, thus enabling one to form a continuous plasma over a wide range of low to high densities. Thus, there can be realized a plasma processing system that ensures processing under wide plasma conditions including high-speed processing under high density conditions.

Abstract: A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combination. The process is also preferably characterized by performing trimming and drying cleaning in a vacuum environment and may also include steps of inspecting dimensions and contamination in a vacuum environment.

Abstract: Disclosed is a process for fabricating a semiconductor device, which efficiently suppresses a damage layer formed on a base silicon substrate or an interconnection layer and removes a high resistivity layer in the formation of a contact hole, thereby reducing a contact resistance. The contact hole is formed in an etching step of reducing ion energy and an oxygen flow rate as an etching depth progresses, thereby suppressing the damage layer formed on the base. The reduction of the contact resistance is achieved by using a step of removing the high resistivity layer using hydrogen or a hydrogen-containing gas plasma.

Abstract: A technique of dry etching the surface of a wafer by using a dry etching apparatus in which the distance between a wafer and a surface facing the wafer is set to the half or less of the diameter of the wafer is disclosed. Even in the case of using, especially, a wafer having a large diameter, the incident amount of etching reaction by-products in the peripheral portion of the wafer and that in the center portion of the wafer are uniformed. Thus, a uniform etching process over the whole surface of the wafer can be realized.

Abstract: A hole is formed on an insulating film made of silicon oxide by selectively plasma-etching the insulating film with an etching gas containing C5F8, O2, and Ar firstly under a condition in which the deposition property of a polymer layer is weak and secondly under a condition in which that of the polymer layer is strong.

Abstract: There is disclosed a method for fabricating semiconductor devices having a wiring construction consisting of a conductive layer (a copper layer) and an insulating layer (a porous insulator layer with low dielectric constant). A method for wiring forming of semiconductor devices of the present invention comprises at least: a first step for forming a first insulating material layer on a sample; a second step for forming on the first insulating material layer a second insulating material layer with a dielectric constant less than 2.

Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.

Abstract: An etching method capable of obtaining a fine fabricated shape, particularly, a vertical fabricated shape with less bowing upon fabrication of insulation films in the production of semiconductors, the method comprising controlling the incident amount of O, F or N radicals, gas flow rate or consumption amount of O, F and N on the inner wall surface with etching time to suppress excessive O, F and N which become excessive in the initial stage of etching, the method also including control for the flow rate or the consumption amount based on the result of measurement for plasmas during etching so as to obtain a stable etching shape. Since bowing can be reduced upon fabrication of insulation film hole and insulation film while maintaining the etching rate and the selectivity, finer semiconductor device can be produced easily.

Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.

Abstract: Automatic generation of processing conditions will be provided, based on a database and process modeling by a computer equipped in semiconductor device fabrication equipment, by using input of wafer processing history including the thickness and quality. The computer equipped in semiconductor device fabrication equipment obtains the wafer processing and inspection results from a production line management computer in order to assist input of the process history. The computer in the fabrication equipment can be connected to computers in a fabrication equipment manufacturer on a communication network to automatically provide process conditions and maintenance schedule.