Patents by Inventor Masaru Kidoh

Masaru Kidoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100039865
    Abstract: A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.
    Type: Application
    Filed: January 31, 2008
    Publication date: February 18, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kidoh, Hiroyasu Tanaka, Masaru Kito, Ryota Katsumata, Hideaki Aochi, Mitsuru Sato
  • Publication number: 20100038699
    Abstract: A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured.
    Type: Application
    Filed: August 17, 2009
    Publication date: February 18, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20100038703
    Abstract: A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.
    Type: Application
    Filed: July 10, 2009
    Publication date: February 18, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KITO, Masaru KIDOH, Hiroyasu TANAKA, Megumi ISHIDUKI, Yosuke KOMORI, Hideaki AOCHI
  • Publication number: 20100034028
    Abstract: In a nonvolatile semiconductor memory device having n (n is an integer of two or more) electrode films stacked and having charge storage layers provided above and below each of the electrode films, when data “0” is written by injecting electrons into the charge storage layer on a source line side of a memory cell of the number k (k is an integer of 1 to (n?1)) as counted from an end on a bit line side in a selected semiconductor pillar, positive program potential is given to the electrode film of the number 1 to k as counted from the bit line side, and 0 V is given to the electrode film of the number (k+1) to n, therewith positive potential is given to the bit line and 0 V is given to the source line.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 11, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota KATSUMATA, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
  • Publication number: 20100013049
    Abstract: A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase shape, and a first interlayer dielectric film is formed around the first multilayer body. Next, a plurality of contact holes having a diameter decreasing downward are formed in the first interlayer dielectric film so that the contact holes reach respective end portions of the electrode films. Then, a sacrificial material is buried in the contact holes. Next, a second multilayer body is formed immediately above the first multilayer body, and a second interlayer dielectric film is formed around the second multilayer body. Thereafter, a plurality of contact holes having a diameter decreasing downward are formed in the second interlayer dielectric film to communicate with the respective contact holes formed in the first interlayer dielectric film.
    Type: Application
    Filed: July 17, 2009
    Publication date: January 21, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Yoshiaki Fukuzumi, Masaru Kito, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yasuyuki Matsuoka
  • Publication number: 20090321813
    Abstract: A nonvolatile semiconductor memory device includes: a stacked body with a plurality of insulating films and electrode films alternately stacked therein, through which a through hole extending in the stacking direction is formed; a semiconductor pillar buried inside the through hole; and a charge storage layer located on both sides of each of the electrode films in the stacking direction and insulated from the electrode film and the semiconductor pillar.
    Type: Application
    Filed: March 17, 2009
    Publication date: December 31, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru KIDOH, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi
  • Publication number: 20090294844
    Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.
    Type: Application
    Filed: June 3, 2008
    Publication date: December 3, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyasu TANAKA, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
  • Publication number: 20090267135
    Abstract: A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 29, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Hideaki Aochi, Megumi Ishiduki, Yasuyuki Matsuoka
  • Publication number: 20090242967
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.
    Type: Application
    Filed: March 13, 2009
    Publication date: October 1, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryota KATSUMATA, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20090230458
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.
    Type: Application
    Filed: February 25, 2009
    Publication date: September 17, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Megumi ISHIDUKI, Hideaki Aochi, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Yasuyuki Matsuoka
  • Publication number: 20090230459
    Abstract: A non-volatile semiconductor memory device includes a memory string which is electrically rewritable and includes a plurality of memory cells connected in series. The memory string includes a plurality of first conductive layers which are extended parallel to a substrate and laminated; a first semiconductor layer which is formed so as to pass through the plurality of the first conductive layers; and an electric charge accumulation layer which is formed between the first conductive layer and the first semiconductor layer and is configured so as to be able to accumulate electric charge. The first conductive layer is configured by material smaller in work function than P+-type polysilicon.
    Type: Application
    Filed: March 2, 2009
    Publication date: September 17, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaru KITO, Ryota KATSUMATA, Hiroyasu TANAKA, Masaru KIDOH, Yoshiaki FUKUZUMI, Hideaki AOCHI, Yasuyuki MATSUOKA
  • Publication number: 20090230462
    Abstract: Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction.
    Type: Application
    Filed: February 26, 2009
    Publication date: September 17, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Tanaka, Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20090224309
    Abstract: A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so that
    Type: Application
    Filed: February 20, 2009
    Publication date: September 10, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kidoh, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20090212350
    Abstract: A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 27, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaru KIDOH, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Akihiro Nitayama, Hitoshi Ito, Yasuyuki Matsuoka
  • Publication number: 20090179257
    Abstract: A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke Komori, Masaru Kito, Megumi Ishiduki, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 7558141
    Abstract: A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: July 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Masaru Kito, Hideaki Aochi, Yoshiaki Fukuzumi, Yasuyuki Matsuoka
  • Publication number: 20090146206
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells.
    Type: Application
    Filed: November 28, 2008
    Publication date: June 11, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20090146190
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising: a columnar semiconductor layer perpendicularly extending toward a substrate; a plurality of conductive layers being formed in parallel to the substrate and including a first space between a sidewall of the columnar semiconductor layers; and characteristic change layer being formed on the sidewall of the columnar semiconductor layer faced to the first space or a sidewall of the conductive layer faced to the first space and changing characteristics accompanying with applied voltage; wherein the plurality of the conductive layers have a function of a relative movement to a prescribed direction for the columnar semiconductor layer.
    Type: Application
    Filed: December 1, 2008
    Publication date: June 11, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki FUKUZUMI, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 7539056
    Abstract: In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to constitute a first select signal line while control electrodes of second select transistor are integrated to constitute a second select signal line. The second select signal line is displaced from the first select signal line by a half pitch.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: May 26, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Masaru Kito, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kidoh, Mitsuru Sato
  • Publication number: 20090108333
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.
    Type: Application
    Filed: October 29, 2008
    Publication date: April 30, 2009
    Applicant: Kabushiki Kasiha Toshiba
    Inventors: Masaru KITO, Ryota KATSUMATA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Hideaki AOCHI, Yasuyuki MATSUOKA