Patents by Inventor Masaru Kidoh

Masaru Kidoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7969789
    Abstract: In a nonvolatile semiconductor memory device having n (n is an integer of two or more) electrode films stacked and having charge storage layers provided above and below each of the electrode films, when data “0” is written by injecting electrons into the charge storage layer on a source line side of a memory cell of the number k (k is an integer of 1 to (n?1)) as counted from an end on a bit line side in a selected semiconductor pillar, positive program potential is given to the electrode film of the number 1 to k as counted from the bit line side, and 0 V is given to the electrode film of the number (k+1) to n, therewith positive potential is given to the bit line and 0 V is given to the source line.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
  • Publication number: 20110147818
    Abstract: A nonvolatile semiconductor memory device includes: a substrate; a memory multilayer body with a plurality of insulating films and electrode films alternately stacked therein, the memory multilayer body being provided on a memory array region of the substrate; a semiconductor pillar buried in the memory multilayer body and extending in stacking direction of the insulating films and the electrode films; a charge storage film provided between one of the electrode films and the semiconductor pillar; a dummy multilayer body with a plurality of the insulating films and the electrode films alternately stacked therein and a dummy hole formed therein, the dummy multilayer body being provided on a peripheral circuit region of the substrate; an insulating member buried in the dummy hole; and a contact buried in the insulating member and extending in the stacking direction.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 23, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota KATSUMATA, Yoshiaki Fukuzumi, Masaru Kidoh, Masaru Kito, Hideaki Aochi
  • Publication number: 20110127597
    Abstract: A nonvolatile semiconductor memory device with charge storage layers with high reliability is provided. A plurality of insulating films and a plurality of electrode films 14 are alternately stacked on a substrate 11, and a plurality of selection gate electrodes 17 extending in the X direction and a plurality of bit lines BL extending in the Y direction are provided thereon. U-shaped silicon members 33 are provided, each of which is constituted by a plurality of silicon pillars 31 passing through the electrode films 14 and the selection gate electrode 17, whose upper ends are connected to the bit lines BL, and a connective member 32 connecting lower parts of one pair of the silicon pillars 31 disposed in diagonal positions. The electrode film 14 of each layer is divided for the respective selection gate electrodes 17.
    Type: Application
    Filed: July 1, 2009
    Publication date: June 2, 2011
    Inventors: Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Masaru Kito, Ryota Katsumata, Masaru Kidoh
  • Publication number: 20110111579
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 12, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20110103149
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar.
    Type: Application
    Filed: August 5, 2010
    Publication date: May 5, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota KATSUMATA, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Publication number: 20110103153
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
    Type: Application
    Filed: August 5, 2010
    Publication date: May 5, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota KATSUMATA, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 7936004
    Abstract: A nonvolatile semiconductor memory device includes a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; a second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory string and the first to nth electrodes of at least two other memory strings which are adjacent to the memory string in two directions are shared as first to nth conductor layers spread in two dimensions.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: May 3, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 7927926
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: April 19, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20110084331
    Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.
    Type: Application
    Filed: December 17, 2010
    Publication date: April 14, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
  • Publication number: 20110075481
    Abstract: A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.
    Type: Application
    Filed: January 27, 2010
    Publication date: March 31, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Tomoko Fujiwara, Megumi Ishiduki, Yosuke Komori, Yoshimasa Mikajiri, Shigeto Oota, Ryouhei Kirisawa, Hideaki Aochi
  • Patent number: 7910432
    Abstract: Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Tanaka, Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 7910914
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a plurality of memory devices each having: a resistance change element, and a diode connected serially to the resistance change element; and a source conductive layer spreading two-dimensionally to be connected to one ends of the plurality of memory devices.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Tanaka, Ryota Katsumata, Hideaki Aochi, Masaru Kidoh, Masaru Kito, Mitsuru Sato
  • Patent number: 7902591
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20110049608
    Abstract: A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.
    Type: Application
    Filed: March 15, 2010
    Publication date: March 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru KIDOH, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Publication number: 20110033995
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.
    Type: Application
    Filed: October 20, 2010
    Publication date: February 10, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryota KATSUMATA, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20110031550
    Abstract: A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.
    Type: Application
    Filed: March 19, 2010
    Publication date: February 10, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke Komori, Hideaki Aochi, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Publication number: 20110018050
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.
    Type: Application
    Filed: March 19, 2010
    Publication date: January 27, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko FUJIWARA, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Publication number: 20110018052
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.
    Type: Application
    Filed: June 22, 2010
    Publication date: January 27, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Fujiwara, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Publication number: 20110019480
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; a first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer to electrically connect the first and second semiconductor pillars; a connection portion conductive layer opposing the connection portion semiconductor layer; a memory layer, an inner insulating film, and an outer insulating film provided between the first and second semiconductor layers and the electrode films and between the connection portion semiconductor layer and the connection portion conductive layer. At least a portion of a face of the connection portion conductive layer opposing the outer insulating film is a curved surface having a recessed configuration on a side of the outer insulating film.
    Type: Application
    Filed: March 19, 2010
    Publication date: January 27, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru KITO, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Hideaki Aochi
  • Publication number: 20110012188
    Abstract: A semiconductor memory device includes: a stacked body formed of a plurality of inter-layer insulating films and a plurality of electrode films alternately stacked and having a through-hole formed in the stacking direction; an electrode-side insulating film of a film thickness of 4 nm or more provided on an inner surface of the through-hole; a charge storage film provided on the electrode-side insulating film; a semiconductor-side insulating film of a film thickness of 4 nm or more provided on the charge storage film; and a semiconductor pillar buried in the through-hole.
    Type: Application
    Filed: March 22, 2010
    Publication date: January 20, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru KITO, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Hideaki Aochi