Patents by Inventor Masaru Moriwaki

Masaru Moriwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010026978
    Abstract: A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon film formed on the first gate insulating film. The second MOSFET includes a second gate insulating film formed on the semiconductor substrate and having a relatively small thickness and a second gate electrode composed of a metal film made of a refractory metal or a compound of a refractory metal and formed on the second gate insulating film.
    Type: Application
    Filed: May 15, 2001
    Publication date: October 4, 2001
    Inventors: Masaru Moriwaki, Takayuki Yamada
  • Publication number: 20010025972
    Abstract: After an insulating film serving as a gate insulating film is formed on a semiconductor substrate, a titanium nitride film is deposited by chemical vapor deposition on the insulating film. Then, a tungsten film is deposited by sputtering on the titanium nitride film. Subsequently, a multilayer film composed of the tungsten film and the titanium nitride film is patterned to form a gate electrode composed of the multilayer film.
    Type: Application
    Filed: January 16, 2001
    Publication date: October 4, 2001
    Inventors: Masaru Moriwaki, Takayuki Yamada, Kazuhiko Yamamoto
  • Publication number: 20010008846
    Abstract: A video game device in which a game screen displayed on a monitor is controlled by operating an operation unit, the video game device comprises a character display control unit for displaying a player character in such a manner as to be rotatable together with a throwing object character and making such a display that the throwing object character is thrown in a specified direction by the player character when the operation unit is operated at a specified timing, and a guide display control unit for setting a guide display area in a partial area of the game screens, displaying a throwing mark in the guide display area which mark moves in response to a rotation of the throwing object character, and displaying an area mark specifying a throwing area of the throwing object character in association with the guide display area.
    Type: Application
    Filed: January 18, 2001
    Publication date: July 19, 2001
    Applicant: KONAMI CORPORATION
    Inventors: Madoka Yamauchi, Masaru Moriwaki
  • Patent number: 6069055
    Abstract: The fabricating method for semiconductor devices in which the trench technique is employed to perform isolation between devices, and which comprises the steps of sequentially depositing a first film 2, 3 and a second film 4 on top of a silicon substrate 1, forming an element isolation trench 5 in the silicon substrate 1 with masking of the first film 2, 3 and second film 4 which have undergone patterning, and growing a silicon oxide film 6 that is generated by reaction of ozone and tetra-ethyl-ortho-silicate inside the element isolation trench where silicon is exposed.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: May 30, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takaaki Ukeda, Toshiki Yabu, Takashi Uehara, Mizuki Segawa, Masatoshi Arai, Masaru Moriwaki
  • Patent number: 6034416
    Abstract: The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: March 7, 2000
    Assignee: Matsushita Electirc Industrial Co., Ltd.
    Inventors: Takashi Uehara, Toshiki Yabu, Mizuki Segawa, Takaaki Ukeda, Masatoshi Arai, Masaru Moriwaki