Abstract: After initializing a Direct Rambus DRAM under test with initialization data, an address, pattern data and mask data are provided to the memory to effect therein a byte-wise masked write of the pattern data, and parallel mask data is converted to plural pieces of serial mask data in accordance with burst addresses generated in a burst address generating means. Based on the bit logical value of each serial mask data, it is decided whether data of each byte is write-enabled or not in the byte-wise masked write, based on the bit logical value of each serial mask data and either one of the initialization data and the byte-wise masked written pattern data is selected to generate expectation data.

Abstract: A pattern generator that generates a test pattern used for testing an electric part including: a pattern memory that stores test pattern information, which defines the test pattern; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the test pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory, which is different from the vector memory, that stores an interruption vector instruction which indicates an order for reading out the interruption test pattern information from the interruption pattern memory; an interruption address expansion unit that generates an address of the interruption test pattern information according to th

Abstract: A test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for alternately storing vector instructions read out from vector memory and bank memories; an address expander for generating an address of each of control instructions in control memory in accordance with vector instructions stored in a plurality of bank memories; and a test pattern calculator for generating test patterns based on control instructions read out from an address generated by an address expander stored in the control memory.

Abstract: A pattern generator generates parallel pattern data and applies it to packet generating parts provided corresponding to row-address and column-address pins of a memory device under test. The pattern generator contains a packet select signal generating part that generates two packet select signals for generating respective cycle numbers in a sequence of cycles in an arbitrary packet period. In data setting parts provided corresponding to the row-address and column-address pins, respectively, bit positions of the data to be fed to the corresponding pins in the parallel pattern data are prestored in correspondence with the cycle numbers. In each cycle the bit positions corresponding to the cycle number are read out by the packet select signals corresponding to the row-address and column-address pins, and in the corresponding packet generating parts data bits corresponding to their bit positions in the parallel pattern data are selected and provided to the corresponding pins.

Abstract: A pattern generator generates parallel pattern data and applies it to packet generating parts provided corresponding to row-address and column-address pins of a memory device under test. The pattern generator contains a packet select signal generating part that generates two packet select signals for generating respective cycle numbers in a sequence of cycles in an arbitrary packet period. In data setting parts provided corresponding to the row-address and column-address pins, respectively, bit positions of the data to be fed to the corresponding pins in the parallel pattern data are prestored in correspondence with the cycle numbers. In each cycle the bit positions corresponding to the cycle number are read out by the packet select signals corresponding to the row-address and column-address pins, and in the corresponding packet generating parts data bits corresponding to their bit positions in the parallel pattern data are selected and provided to the corresponding pins.

Abstract: An address signal, a device control signal and a test pattern data outputted from a pattern generating part are applied to a semiconductor device under test, a response output signal from the semiconductor device under test is compared by a logical comparison part with an expected value data outputted from the pattern generating part, and the logical comparison part generates upon detection of a discordance in the comparison result a failure data representing a failure memory cell, which data is stored together with the address signal, the device control signal and the expected value data outputted from the pattern generating part in a data failure memory, wherein a variable delay part that can give arbitrary time delays to the address signal, the expected value data, and the device control signal, respectively is provided on a data transmission path connecting the pattern generating part to the data failure memory.

Abstract: In a semiconductor memory testing apparatus for testing a DRAM which requires a refresh operation, plural pattern generation parts are operated normally to generate high-speed pattern signals. The plural pattern generation parts are connected to a common sequence control part and controlled by the count value of the same program counter so that they branch to the refresh mode, operate in the refresh mode a plurality of number of times, then return to the main routine and resume the generation of pattern data.

Abstract: It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control per bit. The pattern generator includes an XOR controller (131) which generates a control signal in response to instructions from an instruction memory (112), an AND gate which receives an output signal of the XOR controller (131) at its one terminal and an inverted output signal of a data generator B (15) at its other input terminal, and an exclusive OR gate (121) which receives an output of the AND gate (123) at its one input terminal and an output a data generator A (14) at the other input terminal.

Abstract: It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control per bit. The pattern generator includes an XOR controller (131) which generates a control signal in response to instructions from an instruction memory (112), an AND gate which receives an output signal of the XOR controller (131) at its one terminal and an inverted output signal of a data generator B (15) at its other input terminal, and an exclusive OR gate (121) which receives an output of the AND gate (123) at its one input terminal and an output a data generator A (14) at the other input terminal.