Patents by Inventor Masashi Fujimoto

Masashi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050019708
    Abstract: A phase-shifting mask suppresses increase of the minimum pattern-element size due to optical proximity effect. The mask a first pattern region formed on a transparent substrate, including a first blocking part for forming at least one first pattern element. The mask further includes a second pattern region on the substrate, including second blocking parts forming second pattern elements arranged periodically. The first pattern region includes first phase- and transparent parts. The second pattern region includes second phase-shifting and transparent parts. The intensity of exposing light through the first pattern region is set to be approximately equal to that of the light through the second pattern region. A third blocking part surrounds the first phase-shifting and transparent parts. A fourth blocking part surrounds the second phase-shifting and transparent parts.
    Type: Application
    Filed: August 19, 2004
    Publication date: January 27, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masashi Fujimoto
  • Patent number: 6841890
    Abstract: An alignment mark is arranged to be within an image screen and the alignment mark is formed with rectangular patterns having varied dimensions from each other. The signal waveforms from each of the rectangular patterns are measured. The number of the rectangular patterns with normal waveforms is compared to the minimum required number of marks prescribed beforehand. The amount of deviation in alignment is calculated by excluding the abnormal measured result.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: January 11, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6835652
    Abstract: A via hole 18 is opened in an interlayer insulating film 17, which covers a lower layer interconnect 12, a protective film 19 is embedded on the base portion of the via hole 18, and a soluble resin 20, which dissolves in a resist developing fluid under unexposed conditions, is further embedded thereupon. On this basis, a photoresist 21 is applied, and this photoresist 21 is subjected to an exposure and a development process so as to form a resist pattern 21a, which has an aperture window in a region including the via hole. Upon formation of an interconnective trench in the interlayer insulating film 17 utilizing the resist pattern 21a, a dual damascene structure is formed by embedding a metallic material into the vial hole and interconnective trench.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: December 28, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6812155
    Abstract: A pattern formation method of the present invention is one that forms a circuit pattern in a resist film upon a wafer 141 by exposure using a plurality of phase-shift masks. A first phase-shift mask is for an isolated pattern including a pattern with a distance between adjacent patterns (inter-pattern distance) W1 of at least 400 nm, and a second phase-shift mask is for a dense pattern including patterns with inter-pattern distances W2 under 400 nm. Affects of the optical proximity effect are eliminated through providing optimum exposure conditions for the distances between adjacent patterns W1 and W2 using the plurality of phase-shift masks in accordance with respective inter-pattern distances W1 and W2.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: November 2, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6800402
    Abstract: A phase-shifting mask suppresses increase of the minimum pattern-element size due to optical proximity effect. The mask has a first pattern region formed on a transparent substrate, including a first blocking part for forming at least one first pattern element. The mask further includes a second pattern region on the substrate, including second blocking parts forming second pattern elements arranged periodically. The first pattern region includes first phase-shifting and transparent parts. The second pattern region includes second phase-shifting and transparent parts. The intensity of exposing light through the first pattern region is set to be approximately equal to that of the light through the second pattern region. A third blocking part surrounds the first phase-shifting and transparent parts. A fourth blocking part surrounds the second phase-shifting and transparent parts.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: October 5, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6699626
    Abstract: A mask set has a first mask including a shielding region shielding a first pattern-defining light; a second mask including a phase-shifting region having a phase shifter edge and a non-phase-shifting region adjacent to the phase-shifting region on the phase shifter edge. A first phase of the first light portion passing through the phase-shifting region differs from a second phase of the second light portion. The first and second masks are aligned such that the phase shifter edge overlaps on the shielding region.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: March 2, 2004
    Assignee: NEC Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6670632
    Abstract: A reticle comprises a first area including a desired circuit pattern and a second area including alignment marks arranged at specific positions, the first area and the second area being located in an exposure range of an optical exposure apparatus. Each of the alignment marks comprises mark elements arranged to form a first geometric shape. Each of the mark elements has main sub-elements arranged in a specific direction at first pitches to form a second geometric shape, a first auxiliary sub-element located at one end of the second geometric shape, a second auxiliary sub-element located at the other end of the second geometric shape. The first auxiliary sub-element is apart from a first one of the main sub-elements at a second pitch. The second auxiliary sub-element is apart from a second one of the main sub-elements at a third pitch. Each of the main sub-elements is resolvable in the apparatus. Each of the first and second auxiliary sub-elements is irresolvable in the apparatus.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: December 30, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6645823
    Abstract: A semiconductor manufacturing method employing optical lithography, using a reticle for lithographic alignment. The reticle includes a first area having a desired circuit pattern, and a second area including alignment marks arranged at specific positions, each area being located in an exposure range of an optical exposure apparatus. Each of the alignment marks includes mark elements arranged to form a first geometric shape. Each of the mark elements has main sub-elements arranged in a specific direction at first pitches to form a second geometric shape, and auxiliary sub-elements located at each end of the second geometric shape. Each auxiliary sub-element is apart from one of the main sub-elements at a second pitch. Each main sub-element is optically resolvable, while each auxiliary sub-element is optically irresolvable. Each of the main and auxiliary sub-elements preferably has a linear shape.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: November 11, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Publication number: 20030199131
    Abstract: An alignment mark is arranged to be within an image screen and the alignment mark is formed with rectangular patterns having varied dimensions from each other. The signal waveforms from each of the rectangular patterns are measured. The number of the rectangular patterns with normal waveforms is compared to the minimum required number of marks prescribed beforehand. The amount of deviation in alignment is calculated by excluding the abnormal measured result.
    Type: Application
    Filed: April 8, 2003
    Publication date: October 23, 2003
    Applicant: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Publication number: 20030198896
    Abstract: A via hole 18 is opened in an interlayer insulating film 17, which covers a lower layer interconnect 12, a protective film 19 is embedded on the base portion of the via hole 18, and a soluble resin 20, which dissolves in a resist developing fluid under unexposed conditions, is further embedded thereupon. On this basis, a photoresist 21 is applied, and this photoresist 21 is subjected to an exposure and a development process so as to form a resist pattern 21a, which has an aperture window in a region including the via hole. Upon formation of an interconnective trench in the interlayer insulating film 17 utilizing the resist pattern 21a, a dual damascene structure is formed by embedding a metallic material into the vial hole and interconnective trench.
    Type: Application
    Filed: April 8, 2003
    Publication date: October 23, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masashi Fujimoto
  • Patent number: 6613483
    Abstract: The present invention provides a mask for measuring an optical aberration, the mask including at least a measuring pattern comprising plural pattern parts being separated from each other, wherein the plural pattern parts provide individual widths which are simply increased on first and second directional axes non-parallel to each other and vertical to a plane of the mask, provided that the width of each of the plural pattern parts is unchanged at least on the first and second directional axes.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: September 2, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Publication number: 20030142282
    Abstract: A pattern forming method of the invention for transferring a pattern on a photo-mask onto a photo-sensitive resin film on a substrate using a scan-projection exposure method includes the steps of:
    Type: Application
    Filed: January 28, 2003
    Publication date: July 31, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masashi Fujimoto
  • Publication number: 20030139054
    Abstract: A pattern formation method of the present invention is one that forms a circuit pattern in a resist film upon a wafer 141 by exposure using a plurality of phase-shift masks. A first phase-shift mask is for an isolated pattern including a pattern with a distance between adjacent patterns (inter-pattern distance) W1 of at least 400 nm, and a second phase-shift mask is for a dense pattern including patterns with inter-pattern distances W2 under 400 nm. Affects of the optical proximity effect are eliminated through providing optimum exposure conditions for the distances between adjacent patterns W1 and W2 using the plurality of phase-shift masks in accordance with respective inter-pattern distances W1 and W2.
    Type: Application
    Filed: January 15, 2003
    Publication date: July 24, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masashi Fujimoto
  • Publication number: 20030118919
    Abstract: A mask set has a first mask including a shielding region shielding a first pattern-defining light; a second mask including a phase-shifting region having a phase shifter edge and a non-phase-shifting region adjacent to the phase-shifting region on the phase shifter edge. A first phase of the first light portion passing through the phase-shifting region differs from a second phase of the second light portion. The first and second masks are aligned such that the phase shifter edge overlaps on the shielding region.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 26, 2003
    Applicant: NEC CORPORATION
    Inventor: Masashi Fujimoto
  • Patent number: 6580492
    Abstract: A reticle system includes a reticle film having thereon a plurality of scale patterns each having a plurality of scale marks plotted therein, and a shield film having a plurality of pinholes each disposed corresponding to one of the scale patterns. A light emitted from a point light source having an effective coherent factor “x” and passing the reticle film at a scale mark “x” or below “x” in one of the scale patterns passes through the corresponding pinhole. After transferring the scale patterns onto a wafer surface, the effective coherent factors are read from the maximum scale marks for respective scale patterns on the wafer surface. The dispersion of the coherent factors can be calculated therefrom.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: June 17, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6573015
    Abstract: The present invention provides a mask for measuring an optical aberration, the mask including at least a measuring pattern comprising plural pattern parts being separated from each other, wherein the plural pattern parts provide individual widths which are simply increased on first and second directional axes non-parallel to each other and vertical to a plane of the mask, provided that the width of each of the plural pattern parts is unchanged at least on the first and second directional axes.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 3, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6522389
    Abstract: A scanning exposure system to expose an objective wafer has a light source; a slit-shaped window having a length in a first direction greater than a width in a second direction perpendicular to the first direction; a photomask having an exposure opening therein, the exposure opening having a length along a longer direction greater than a width along a narrower direction perpendicular to the longer direction, the longer direction being aligned parallel to a projection of the first direction on the photomask, the objective wafer being exposed to the light source through the slit-shaped window and the exposure opening during a scanning operation by a relative motion of the photomask with respect to the slit-shaped window in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: February 18, 2003
    Assignee: NEC Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6517982
    Abstract: A method of forming a photoresist pattern by a photolithography technique is composed of: providing a photoresist layer; exposing the photoresist layer to a first pattern-defining light using a first mask; and exposing the photoresist layer to a second pattern-defining light using a second mask. The first mask includes a shielding region shielding the first pattern-defining light. The second mask includes a phase-shifting region having a phase shifter edge and a non-phase-shifting region adjacent to the phase-shifting region on the phase shifter edge. A first light portion of the second pattern-defining light passes through the phase-shifting region. A second light portion of the second pattern-defining light passes through the non-phase-shifting region. A first phase of the first light portion differs from a second phase of the second light portion. The first and second masks are aligned such that the phase shifter edge overlaps on the shielding region.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: February 11, 2003
    Assignee: NEC Corporation
    Inventor: Masashi Fujimoto
  • Publication number: 20030027065
    Abstract: The present invention provides a mask for measuring an optical aberration, the mask including at least a measuring pattern comprising plural pattern parts being separated from each other, wherein the plural pattern parts provide individual widths which are simply increased on first and second directional axes non-parallel to each other and vertical to a plane of the mask, provided that the width of each of the plural pattern parts is unchanged at least on the first and second directional axes.
    Type: Application
    Filed: September 27, 2002
    Publication date: February 6, 2003
    Applicant: NEC CORPORATION
    Inventor: Masashi Fujimoto
  • Publication number: 20020155356
    Abstract: The present invention provides a mask for measuring an optical aberration, the mask including at least a measuring pattern comprising plural pattern parts being separated from each other, wherein the plural pattern parts provide individual widths which are simply increased on first and second directional axes non-parallel to each other and vertical to a plane of the mask, provided that the width of each of the plural pattern parts is unchanged at least on the first and second directional axes.
    Type: Application
    Filed: March 5, 2001
    Publication date: October 24, 2002
    Applicant: NEC CORPORATION
    Inventor: Masashi Fujimoto