Abstract: A circuit board which comprises a conductive pattern section 4 with a pattern formed on a conductive layer 3 provided on a board main body 2, wherein two or more bonding positions 6a, 6b, 6c that bumps of a part mounted by ultrasonic bonding strike are set in the conductive pattern section 4, characterized in that a notch part 8a or a recess extending from the margin of the conductive pattern section 4 to the inside thereof and reaching the proximity of the bonding position or an isolated notch part 8b or recess is formed in the conductive layer in the proximity of at least one bonding position.

Abstract: A resin package fabrication processes comprises three steps. At the first step, a thermosetting resin-containing resin substrate is machined. At the second step carried out after the first step, the resin substrate is heated to an original glass transition temperature that the resin substrate has or a temperature that is higher than the glass transition temperature so that the glass transition temperature that the resin substrate has is elevated to a new glass transition temperature. At the third step, a resin layer is placed on at least a portion of the resin substrate to which the new glass transition temperature is imparted, and the resin substrate with the resin layer placed on that portion is then heated to the original glass transition temperature or a temperature between the original glass transition temperature and the new glass transition temperature, thereby fixing the resin layer to the resin substrate.

Abstract: An electronic element is mounted on a resin wiring substrate and a cover member is bonded to the wiring substrate so as to cover the electronic element and constitute an encapsulation region. The encapsulation region houses the electronic element and has a cavity inside. A side electrode is formed of an electronically conductive through groove provided in a cover-member-bonding surface on the wiring substrate. A plating layer inside the electrically conductive through groove includes at least two metal layers including an Au plating layer and a Cu plating layer. The plating layer has conductors connected to circumferential peripheries of the electrically conductive through groove on upper and lower surfaces of the wiring substrate. Only the Cu plating layer is formed on the conductor on the upper surface of the wiring substrate to improve the reliability of bonding.

Abstract: A chip junction nozzle in that opposite slant planes 43 which come into contact with edges of 2 sides of the chip in parallel centering around a nozzle center, and a vacuum suction hole 42 opened in the nozzle center are provided, and the slant plane 43 is formed into a mirror surface having the surface hardness more than HrC40. Further, when the surface roughness of the mirror surface is expressed by the average roughness of the center line, the average roughness of the center line is not more than 1.6 &mgr;m.

Abstract: A through hole 5 formed in a substrate and having an electrode film on an inner surface thereof is cut and divided into two through holes or blind holes each of substantially semicircular arc shape through dicing processing using a rotating blade, and one of the-divided through holes 5 of substantially semicircular arc shape is used as an external connection terminal 3 of substantially semicircular concave arc shape thereby to form a surface mounted electronic parts having a plurality of the external connection terminals 3. The height H of the substantially semicircular arc formed at an inner surface of each of the external connection terminals is set to be equal to or smaller than a value obtained by subtracting twice a thickness t of the electrode film from a radius R of a curvature of the arc.

Abstract: In a chip device in which not only an electrode pattern 25 is provided on a main mounting surface 21a of a base 21 but also bump electrodes 22 are provided as external electrodes for face-down mounting, an electrically insulating layer 31 is provided to be put on at least a part of the main mounting surface 21a so as to remain edge portions which do not cover at least a part of the electrode pattern 25, and a protection layer 32 for protecting the main mounting surface is further provided at a distance from the main mounting surface 21a so as to be put on the electrically insulating layer 31, so that the bump electrodes 22 are connected to the electrode pattern 25 while being in contact with the edge portions of the electrically insulating layer 31 and the protection layer 32.

Abstract: A wiring board having a conductor layer formed on a substrate and a connecting pad disposed in a connecting pad disposition portion provided in part of the conductor layer surface, the conductor layer having a resin inflow prevention portion which is provided adjacently to the said connecting pad disposition portion and which has a surface roughness greater than the surface roughness of the said connecting pad disposition portion, the resin inflow prevention portion being capable of overcoming the problem of prior art that an adhesive resin (resin layer) of a prepreg or an adhesive flows out onto the upper surface of the pad, due to its softening under heat and its being pressurized for bonding when a structure member such as a cover layer is bonded to the wiring board, and forms a cured resin which extremely inhibits the bonding property of a chip element onto the pad.

Abstract: A chip junction nozzle in that opposite slant planes 43 which come into contact with edges of 2 sides of the chip in parallel centering around a nozzle center, and a vacuum suction hole 42 opened in the nozzle center are provided, and the slant plane 43 is formed into a mirror surface having the surface hardness more than HrC40. Further, when the surface roughness of the mirror surface is expressed by the average roughness of the center line, the average roughness of the center line is not more than 1.6 &mgr;m.

Abstract: In a chip device in which not only an electrode pattern 25 is provided on a main mounting surface 21a of a base 21 but also bump electrodes 22 are provided as external electrodes for face-down mounting, an electrically insulating layer 31 is provided to be put on at least a part of the main mounting surface 21a so as to remain edge portions which do not cover at least a part of the electrode pattern 25, and a protection layer 32 for protecting the main mounting surface is further provided at a distance from the main mounting surface 21a so as to be put on the electrically insulating layer 31, so that the bump electrodes 22 are connected to the electrode pattern 25 while being in contact with the edge portions of the electrically insulating layer 31 and the protection layer 32.