Abstract: The present invention is intended to provide a radio transmitter capable of in event that an analysis result of a radio signal to be transmitted is incompliant with a predetermined standard, stopping the radio signal transmission and outputting an abnormal alarm.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: A frequency conversion circuit for changing a frequency of an input signal to obtain an output signal, includes: a sum holding unit holding a sum; an integrating unit updating the sum by changing the sum by a natural number a in one direction at each input of a first predetermined signal based on the input signal; and an output signal generating unit outputting a second predetermined signal as the output signal at each time at which the sum has gone over (b*N+c), where N is an integer, c is a constant integer and b is a natural number equal to or larger than a.

Abstract: An equalizer and an equalization method are provided which are capable of suppressing distortion specific to radio unit, and reducing both the oversampling number and the amount of calculations without causing characteristic deterioration.

Abstract: An equalizer and equalization method as well as a receiver and reception method are provided which have little deterioration of the error rate characteristic even at a low oversampling rate in order to overcome the disadvantages of symbol synchronization and demodulation processing at a high oversampling rate, which is the problem of the QAM system. The equalizer equalizes a detection signal obtained by detecting a transmission signal with periodically inserted known symbol patterns made up of at least one symbol.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: The memory device has an electrically rewritable nonvolatile memory used as a storage medium. To promote even deterioration throughout the memory, the erasing time and writing time are measured, the influence of scatter of cells in the memory are eliminated on the basis of the resultant measurement values and a degree of deterioration is determined with a high accuracy, whereby a memory device of a high reliability and high efficiency is realized. In order to rewrite the nonvolatile memory, therefore, the memory measures erasing time and writing time, compares erasing time with stored reference time, compares the writing time from the comparison results, and determines the degree of deterioration from the correction results. Accordingly, control is possible such that, successively, the more heavily deteriorated part of the memory is used less frequently while the less deteriorated part is used more frequently.

Abstract: A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.

Abstract: High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N−1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N-th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N−1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N-th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N-th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e.

Abstract: In a memory device using an electrically rewritable nonvolatile memory as a storage medium, wherein, in order to allow the memory to deteriorate evenly, the erasing time and writing time are measured, the influence of scatter of cells in the memory being eliminated on the basis of the resultant measurement values, a substantial degree of deterioration being thereby determined with a high accuracy, whereby a memory device of a high reliability and a high efficiency is practically obtained. In order to rewrite an electrically rewritable nonvolatile memory (1), there are provided a means for measuring the erasing time and writing time, a means for comparing an erasing time with a stored reference time, a means for correcting writing time on the basis of the results of the comparison, and a means for determining deterioration on the basis of the results of the correction.

Abstract: High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N−1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N−th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N−1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N−th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N−th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e.

Abstract: A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.

Abstract: In a memory device using an electrically rewritable nonvolatile memory as a storage medium, wherein, in order to allow the memory to deteriorate evenly, the erasing time and writing time are measured, the influence of scatter of cells in the memory being eliminated on the basis of the resultant measurement values, a substantial degree of deterioration being thereby determined with a high accuracy, whereby a memory device of a high reliability and a high efficiency is practically obtained. In order to rewrite an electrically rewritable nonvolatile memory (1), there are provided a means for measuring the erasing time and writing time, a means for comparing an erasing time with a stored reference time, a means for correcting writing time on the basis of the results of the comparison, and a means for determining deterioration on the basis of the results of the correction.

Abstract: High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N-1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N-th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N-1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N-th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N-th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e.