Abstract: An electron-beam cured sheet-type foam comprises: a polypropylene type resin (A) of 100 parts by weight of which main component is polypropylene; a copolymer resin (B) of 5 to 40 parts by weight which is made of ethylene and at least one selected from the group consisting of acrylic acid, ethylacrylate maleic acid anhydride and vinylacetate; and a copolymer resin (C) made of ethylene and an .alpha.-olefin of 4 to 8 carbon atoms, having a melting point of 117.degree. C. to 123.degree. C. and a density of 0.890 g/cm.sup.3 to 0.910 g/cm.sup.3. This foam contains 20 to 60 percent in gel content and has an expansion ratio of 5 to 40.

Abstract: In a semiconductor integrated circuit device of master slice approach according to this invention, regions on basic elements which are not used and isolation areas serve as wiring regions. Resistive elements are formed on the regions on the basic elements which are not used and the isolation areas. A high integration level can be obtained, circuit layout can be facilitated, and versatility of circuit design can be improved.

Abstract: A filter connector comprises a connector body which includes a conductive shell and an insulating insert provided in the conductive shell and having a plurality of through holes. First ends of upper first terminal pins are inserted in the through holes of the insert. Second ends of the first terminal pins pass out the back of the connector body. At least one of the plurality of terminal pins is adapted to support a printed circuit board. The printed circuit board has a conductive pattern which is electrically connected with at least one of the upper first terminal pins. A second terminal pin is electrically connected to the conductive pattern, whereby the second terminal pin is electrically connected with at least one of the first terminal pins. A plurality of filter elements are inserted in a current path between at least one of the first terminal pins and the second terminal pin.

Abstract: A digital-to-analog convertor divides an input digital signal into a least significant bit group and a most significant bit group. The most significant bit group is converted using pulse amplitude modulation and the least significant bit group is converted using pulse width modulation, in which the pulse widths are varied symmetrically about predetermined time points within a conversion period in order to improve the linearity of the pulse width modulation conversion.

Abstract: A logic circuit adapted for fabrication as an integrated circuit is formed having a differential amplifier operating with a constant current source and an appropriate voltage source, and having output transistors to provide the necessary output voltages, does not require a reference voltage input to the differential amplifier, thus, reference voltage transistors are not required. The two binary input signals are selected to have the same amplitude difference between the high and low levels thereof and one of the two input signals is shifted relative to the other one by the amount substantially equal to 1/2 the selected amplitude difference, and the output signals are similarly level shifted. Using this basic logic circuit as a building block other, more complex, logic circuits can be obtained.

Abstract: An integrated injection logic circuit having constant current source transistors and switching inverter transistors. The injector thereof is directly connected to a first reference potential point and the wall thereof is connected through a bias resistor or constant current source to a second reference potential point.

Abstract: An analog-to-digital converter for converting an analog input signal to a digital output signal with m upper bits and n lower bits includes at least 2.sup.m+n -1 resistors connected in a series circuit to a voltage source for establishing respective reference voltages; switch elements selectively coupled to the analog input signal and the resistors in response to a switch control signal for supplying a signal indicative of the analog input signal and the respective reference voltages; at least 2.sup.m -1 upper bit comparators for generating the switch control signal and output signals indicative of the m upper bits, with first inputs receiving the analog input signal and second inputs connected to the series circuit at intervals defining groups of the resistors; an upper bit encoder receiving the output signals from the upper bit comparators and generating the m upper bits; at least 2.sup.

Abstract: An analog-to-digital converter for converting an analog input signal to a digital output signal with m upper bits and n lower bits includes 2.sup.m+n -1 resistors establishing 2.sup.m+n reference voltages for comparison with an amplitude of the analog input signal, 2.sup.m -1 voltage comparing circuits for comparing the analog input signal with 2.sup.n step-by-step reference voltages, a first encoder for encoding the output signals of the 2.sup.m-1 voltage comparing circuits for generating m upper bits of the digital output signal, a matrix circuit having 2.sup.m (2.sup.n -1) voltage comparators for comparing the analog input signal with the remaining reference voltages of the 2.sup.m+n references voltages, the other voltage comparing circuits being supplied output signals of the matrix circuit and a second encoder for encoding output signals of the other voltage comparing circuits for generating n lower bits of the digital output signal.

Abstract: A latched comparator circuit is disclosed in which a voltage comparator circuit of a differential construction composing a part of the latched comparator circuit is substituted for by a plurality of differential amplifying circuits connected in parallel to the prior stage thereof and which are supplied with a differential input. Also, there is disclosed a latched comparator circuit in which a voltage comparator circuit of a differential construction composing a part of the latched comparator circuit is substituted for by a plurality of differential amplifying circuits connected in parallel to the prior stage thereof that are supplied with a differential input for voltage comparison and in which a switching circuit is provided between the differential amplifying circuits and a latch circuit for electrically separating both of them upon latch operation.

Abstract: A digital-to-analog converter of the current-adding kind includes n input buffer circuits to which the bits of the digital signal are applied in parallel, a first ladder resistor network having n resistors connected in series to which complementary outputs of the input buffer circuit are connected, a second ladder resistor network for dividing output terminal voltages from the first ladder resistor network into 2(2.sup.n -1) voltages, (2.sup.n -1) switching circuits having inputs connected to voltage dividing points of the second resistor network, and a common summing resistor connected to the outputs of the switching circuits to add currents supplied thereto, thereby providing an analog voltage having a level corresponding to the numerical value of the digital input signal.

Abstract: An electronic component series wherein a plurality of parallel lead type electronic components (1) each having two parallel lead wires (4) are equispaced along a retainer band (2) and distributed along the length of the retainer band (2) with the lead wires (4) extending in the same direction and are positioned by the retainer band (2), whereby the electronic components (1) are retained. The electronic component series is characterized in that the distance (A) between the pair of lead wires (4) of each electronic component (1) in a region (4a) where the lead wires (4) are placed on the retainer band (2) is made different from that (B) in a region (4c) closer to the electronic component main body (3), while the intermediate portions (4b) of the lead wires (4) are bent to absorb the difference in dimension between the distances (A, B).

Abstract: An oscillator which includes a DC voltage source, a differential amplifier having a hysteresis characteristics, a current source circuit producing a predetermined constant current, a current sink circuit flowing therein substantially one half of the predetermined constant current, and first and second current switching circuits controlled by the output of the hysteresis amplifier to charge/discharge a capacitor by the current from current source/sink circuits, thereby to produce an output pulse signal.

Abstract: An integrating digital-to-analog converter circuit includes an operational-amplifier based integrator, a plurality of constant current sources each providing constant current at a respective different level, and a plurality of switches each associated with a respective current source for coupling the same to the integrator. A plurality of digital counters are arranged to hold a predetermined portion of an n-bit digital word loaded therein and to count clock pulses until their contents reach a predetermined count. At those times, a carry pulse is generated in each such digital counter and the associated switch is opened to cut off the associated current source. Such a digital-to-analog converter circuit can convert data words of relatively high bit length without the need for an excessively high frequency clocking signal.

Abstract: A shift register having a plurality of flip-flop circuits connected in cascade in which a clock pulse is supplied to the flip-flop circuit at the final stage and the AND-outputs from the respective stage of flip-flop circuits are supplied to the preceding stage of flip-flop circuits as clock pulses, whereby the input data are shifted or transferred in synchronism with the clock pulse.

Abstract: A flip-flop circuit is disclosed which has a first semiconductor region of a first conductivity type, injector and base regions of a second conductivity type in the first region, and collector region of the first conductivity type in the base region. In this case, the first, base and collector regions constitute a gate transistor, two of the gate transistors constitute a flip-flop circuit, and each of the transistors has a predetermined distance relation among the injector and collector regions and base contacts in such a manner that the inherent difference of ON and OFF speeds between the transistors causes the flip-flop circuit to operate without causing unnecessary delay.

Abstract: A single pickup head generates an alternating signal proportional to the rotational speed of a DC motor which can be rotated in either of two directions, and such alternating signal is employed by speed and/or phase control circuits to control the motor speed relative to a reference speed in a selected one of the two directions. An overspeed sensing circuit detects speed runaway, which can occur when the motor is rapidly rotated in the direction opposite to the selected direction, and the overspeed sensing circuit then interrupts the motor drive voltage until the motor speed decreases to below its normal speed. At and below normal speed in the undesired direction, the normal torque acts in the selected direction to rapidly reverse the direction and to accelerate the motor to normal speed in the selected direction.

Abstract: A peak detector having rise-time enhancement of input signals is comprised of a feedback amplifier including two input terminals and a feedback circuit which interconnects the amplifier output terminal with one of the input terminals; and a peak detecting circuit, including a capacitor, coupled to the other of the amplifier input terminals. The capacitor voltage is applied as an input signal to the feedback amplifier, and abrupt changes in the rise-time portion of the input signals are detected and are used to vary the amplifier feedback so as to enhance the output signal produced by the amplifier during the rise-time portion.

Abstract: Signal voltage to be limited is applied across a voltage divider comprising a resistor and a controllable impedance element that includes a pair of transistors. The emitter-collector circuit of the transistors is connected in parallel but in opposite polarity, and the output signal voltage is obtained across the controllable impedance element. For limiter operation, a feedback circuit produces a control current based on a signal voltage and applies the control current to the bases of the transistors to control the impedance thereof. When limiter operation is not desired, elements in the feedback circuit are grounded to reduce the controlled current to leakage value. Even the leakage current is prevented from reaching the bases of the transistors by means of a circuit rendered non-conductive in series with the control current circuit.

Abstract: A switching circuit is disclosed in which a first field effect transistor (which will be hereinafter referred to as an FET simply) is provided in such a manner that its source-drain are connected between an input terminal and output terminal and its source and drain electrodes are connected to a bias source through resistors, and a second FET of a source follower type is provided such that its gate electrode is connected to the source electrode of the first FET and its source electrode is connected to the gate electrode of the first FET. In this case, by changing the source electrode voltage level of the second FET, the first FET is made on and off to perform a switching operation.