Patents by Inventor Masashi Tsubuku

Masashi Tsubuku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9685563
    Abstract: A semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, a source electrode in contact with the second oxide semiconductor film, a drain electrode in contact with the second oxide semiconductor film, a metal oxide film over the second oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the metal oxide film, and a gate electrode over the gate insulating film. The metal oxide film contains M (M represents Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) and Zn. The metal oxide film includes a portion where x/(x+y) is greater than 0.67 and less than or equal to 0.99 when a target has an atomic ratio of M:Zn=x:y.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 20, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Toshihiko Takeuchi, Yasumasa Yamane, Masashi Oota
  • Publication number: 20170170326
    Abstract: A transistor in which a change in characteristics is small is provided. A circuit, a semiconductor device, a display device, or an electronic device in which a change in characteristics of the transistor is small is provided. The transistor includes an oxide semiconductor; a channel region is formed in the oxide semiconductor; the channel region contains indium, an element M, and zinc; the element M is one or more selected from aluminum, gallium, yttrium, tin, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium; a gate insulator contains silicon and oxygen whose atomic number is 1.5 times or more as large as the atomic number of silicon; the carrier density of the channel region is higher than or equal to 1×109 cm?3 and lower than or equal to 5×1016 cm?3; and the energy gap of the channel region is higher than or equal to 2.7 eV and lower than or equal to 3.1 eV.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 15, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi TSUBUKU, Kazuya SUGIMOTO, Tsutomu MURAKAWA, Motoki NAKASHIMA, Shinpei MATSUDA, Noritaka ISHIHARA, Daisuke KUROSAKI, Toshimitsu OBONAI, Hiroshi KANEMURA, Junichi KOEZUKA
  • Patent number: 9680028
    Abstract: The concentration of impurity elements included in an oxide semiconductor film in the vicinity of a gate insulating film is reduced. Further, crystallinity of the oxide semiconductor film in the vicinity of the gate insulating film is improved. A semiconductor device includes an oxide semiconductor film over a substrate, a source electrode and a drain electrode over the oxide semiconductor film, a gate insulating film which includes an oxide containing silicon and is formed over the oxide semiconductor film, and a gate electrode over the gate insulating film. The oxide semiconductor film includes a region in which the concentration of silicon is lower than or equal to 1.0 at. %, and at least the region includes a crystal portion.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: June 13, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Patent number: 9673337
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 6, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
  • Patent number: 9666678
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
  • Publication number: 20170148925
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI
  • Patent number: 9647132
    Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, ? is a constant with a unit of time, and ? is a constant greater than or equal to 0.4 and less than or equal to 0.6.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Masashi Tsubuku, Kazuaki Ohshima, Masashi Fujita, Daigo Shimada, Tsutomu Murakawa
  • Patent number: 9640642
    Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: May 2, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hitoshi Nakayama, Masashi Tsubuku, Daigo Shimada
  • Patent number: 9640670
    Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: May 2, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshinari Sasaki, Junichiro Sakata, Masashi Tsubuku
  • Patent number: 9633710
    Abstract: Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 25, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Masashi Fujita
  • Publication number: 20170092776
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel fog nation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
    Type: Application
    Filed: December 8, 2016
    Publication date: March 30, 2017
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE, Kei TAKAHASHI, Kouhei TOYOTAKA, Masashi TSUBUKU, Kosei NODA, Hideaki KUWABARA
  • Patent number: 9601562
    Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Masashi Oota
  • Patent number: 9601633
    Abstract: An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time ?1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Inoue, Masashi Tsubuku, Suzunosuke Hiraishi, Junichiro Sakata, Erumu Kikuchi, Hiromichi Godo, Akiharu Miyanaga, Shunpei Yamazaki
  • Patent number: 9601632
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 9601516
    Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yoshiaki Oikawa, Shunpei Yamazaki, Junichiro Sakata, Masashi Tsubuku, Kengo Akimoto, Miyuki Hosoba
  • Patent number: 9595435
    Abstract: To form an oxide semiconductor film with a low density of localized levels. To improve electric characteristics of a semiconductor device including the oxide semiconductor. After oxygen is added to an oxide film containing In or Ga in contact with an oxide semiconductor film functioning as a channel, heat treatment is performed to make oxygen in the oxide film containing In or Ga transfer to the oxide semiconductor film functioning as a channel, so that the amount of oxygen vacancies in the oxide semiconductor film is reduced. Further, an oxide film containing In or Ga is formed, oxygen is added to the oxide film, an oxide semiconductor film is formed over the oxide film, and then heat treatment is performed.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: March 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Ryosuke Watanabe, Noritaka Ishihara, Masashi Oota
  • Publication number: 20170062620
    Abstract: A novel oxide semiconductor is provided. An oxide semiconductor contains In, an element M (M represents Al, Ga, Y, or Sn), and Zn. The oxide semiconductor has little characteristics variation and structure change and has high electron mobility in the case where the atomic ratio of In to M and Zn in the oxide semiconductor ranges from 4:2:3 to 4:2:4.1 or is a neighborhood thereof.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 2, 2017
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Masashi OOTA, Akihisa SHIMOMURA, Yasumasa YAMANE
  • Patent number: 9583509
    Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: February 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Masayuki Sakakura, Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama, Masashi Tsubuku
  • Patent number: 9583570
    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10?3/cm in an energy range of 1.5 eV to 2.3 eV.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: February 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Ryosuke Watanabe, Masashi Oota, Noritaka Ishihara, Koki Inoue
  • Publication number: 20170054034
    Abstract: A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×1014/cm3 or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.
    Type: Application
    Filed: August 29, 2016
    Publication date: February 23, 2017
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Masashi Tsubuku, Kosei Noda